I3CxBSTAT

I3CxBSTAT

Bus Status

Notes:
  1. 1.Will not self-clear after the event. The user must clear this bit to re-arm.
  2. 2.Refer to section Error Detection and Recovery in SDR Mode for TE0-TE6 Error definitions.
  3. 3.In case of a race condition, user writes always take precedence over hardware events.
0x087, 0x0B8 8     1index x
Parent topic: Register Definitions: I3C Control

I3CxBSTAT

Bit  7 6 5 4 3 2 1 0  
    TE6ERR TE5ERR TE4ERR TE3ERR TE2ERR TE1ERR TE0ERR  
Access    R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS  
Reset    0 0 0 0 0 0 0  

Bit 6 – TE6ERR: TE6 Error Detection(1)

TE6 Error Detection(1)

ValueDescription
1 TE6 Error detected
0 TE6 Error not detected

Bit 5 – TE5ERR: TE5 Error Detection(1)

TE5 Error Detection(1)

ValueDescription
1 TE5 Error detected
0 TE5 Error not detected

Bit 4 – TE4ERR: TE4 Error Detection(1)

TE4 Error Detection(1)

ValueDescription
1 TE4 Error detected
0 TE4 Error not detected

Bit 3 – TE3ERR: TE3 Error Detection(1)

TE3 Error Detection(1)

ValueDescription
1 TE3 Error detected
0 TE3 Error not detected

Bit 2 – TE2ERR: TE2 Error Detection(1)

TE2 Error Detection(1)

ValueDescription
1 TE2 Error detected
0 TE2 Error not detected

Bit 1 – TE1ERR: TE1 Error Detection(1)

TE1 Error Detection(1)

ValueDescription
1 TE1 Error detected
0 TE1 Error not detected

Bit 0 – TE0ERR: TE0 Error Detection(1)

TE0 Error Detection(1)

ValueDescription
1 TE0 Error detected
0 TE0 Error not detected