CLCnPOL

CLCnPOL

Signal Polarity Control Register
  0x1A6 8  

CLCnPOL

Bit  7 6 5 4 3 2 1 0  
  POL       G4POL G3POL G2POL G1POL  
Access  R/W       R/W R/W R/W R/W  
Reset  0       x x x x  

Bit 7 – POL: CLCxOUT Output Polarity Control

CLCxOUT Output Polarity Control

ValueDescription
1 The output of the logic cell is inverted
0 The output of the logic cell is not inverted

Bits 0, 1, 2, 3 – GyPOL: Gate Output Polarity Control

Gate Output Polarity Control

ValueDescription
1 The gate output is inverted when applied to the logic cell
0 The output of the gate is not inverted