Virtual Port Output and Data Register

The output of the Virtual Port is available through the RWn virtual pins. The status of these virtual pins can be read using the PORTW data register.

PORTW is a bidirectional port register. However, unlike a typical I/O port, PORTW consists of two different registers internally which are not user-accessible – ‘PORTW read’ and ‘PORTW write’ registers as shown in Figure 1. Reading from the PORTW register returns result from the ‘PORTW read’ register, which reads the selected Virtual Port input (as per PORTWINx selection). Writing to the PORTW register writes to the ‘PORTW write’ register, which is the actual data register. While the PORTW register can be read any time, writes to the PORTW register can only happen when the clock to the module is disabled (PWCLKEN = 0).

The ‘PORTW write’ register is enabled using DFn bits in the PORTWDF register. The PORTWDF register controls whether the Virtual Port input is connected to the flip-flop (data register) or not. When enabled, the input from the PORTWINx selection is routed through the ‘PORTW write’ register (data register) to the output. When disabled, the Virtual Port input is directly connected to the output, thus creating a completely asynchronous path between the input and output of the Virtual Port. Each bit in the PORTWDF register can individually enable/disable the flip-flop for each bit in the Virtual Port. See Figure 1 for details.

Unlike a typical I/O port, the ‘PORTW write’ register can be clocked by various clock sources. Refer to the Virtual Port Clock section for more details. When the clock to the module is disabled (PWCLKEN = 0), the ‘PORTW write’ register is clocked using the instruction clock (FOSC/4), which allows PORTW write operations in software. This allows software to initialize the state of a virtual pin before the clock is enabled. When the module clock is enabled (PWCLKEN = 1), the ‘PORTW write’ register is clocked using the clock input from the PORTWCLK register selection. This prevents any software writes to the ‘PORTW write’ register (data register). In this case, the ‘PORTW write’ register can only be written through the Virtual Port input from PORTWINx register selection. This allows the formation of hardware-based state machines by interconnecting multiple core independent peripherals through a flip-flop to the output using a specific clock.

In addition to the ‘PORTW read’ register, the Virtual Port outputs (RWn virtual pins) are also routed through PPS and are available for use by other modules as PPS inputs. See the “PPS Inputs” section in the “PPS – Peripheral Pin Select Module” chapter for more information.

  1. 1.Reading PORTW from ‘PORTW read’ register reads the value of the ‘PORTW write’ data register only when the flip-flop is enabled for the corresponding bit using the PORTWDF register. If the flip-flop is disabled, an asynchronous path is created and ‘PORTW read’ reads the unlatched value as per the PORTWINx input selection.
  2. 2.There must be one instruction cycle delay between write and read of the PORTW register, otherwise the previously written value will be read. This is because it takes one clock for the data to be latched from the ‘PORTW write’ register to the ‘PORTW read’ register.