IPR1

IPR1

Peripheral Interrupt Priority Register 1
0x47E 8  
Parent topic: Register Definitions: Interrupt Control

IPR1

Bit  7 6 5 4 3 2 1 0  
  DMA3AIP DMA3ORIP DMA3DCNTIP DMA3SCNTIP DMA2AIP DMA2ORIP DMA2DCNTIP DMA2SCNTIP  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  1 1 1 1 1 1 1 1  

Bit 7 – DMA3AIP: DMA3 Abort Interrupt Priority

DMA3 Abort Interrupt Priority

ValueDescription
1 High Priority
0 Low Priority

Bit 6 – DMA3ORIP: DMA3 Overrun Interrupt Priority

DMA3 Overrun Interrupt Priority

ValueDescription
1 High Priority
0 Low Priority

Bit 5 – DMA3DCNTIP: DMA3 Destination Count Interrupt Priority

DMA3 Destination Count Interrupt Priority

ValueDescription
1 High Priority
0 Low Priority

Bit 4 – DMA3SCNTIP: DMA3 Source Count Interrupt Priority

DMA3 Source Count Interrupt Priority

ValueDescription
1 High Priority
0 Low Priority

Bit 3 – DMA2AIP: DMA2 Abort Interrupt Priority

DMA2 Abort Interrupt Priority

ValueDescription
1 High Priority
0 Low Priority

Bit 2 – DMA2ORIP: DMA2 Overrun Interrupt Priority

DMA2 Overrun Interrupt Priority

ValueDescription
1 High Priority
0 Low Priority

Bit 1 – DMA2DCNTIP: DMA2 Destination Count Interrupt Priority

DMA2 Destination Count Interrupt Priority

ValueDescription
1 High Priority
0 Low Priority

Bit 0 – DMA2SCNTIP: DMA2 Source Count Interrupt Priority

DMA2 Source Count Interrupt Priority

ValueDescription
1 High Priority
0 Low Priority