The following section describes the sequence of events that occur when the module is transmitting data in 7-bit Addressing mode:
0
), the
address buffer, I2CxADB1, is enabled. In this case, the 7-bit
client address and R/W bit are loaded into
I2CxADB1, with the R/W bit clear
(R/W = 0
). The number of data
bytes are loaded into I2CxCNT, and the first data byte is loaded into
I2CxTXB. After these registers are loaded, software must set the
Start (S) bit to begin communication. Once the S bit is
set, host hardware waits for the Bus Free (BFRE) bit to be set before transmitting the Start
condition to avoid bus collisions.1
), the address
buffer is disabled. In this case, the number of data bytes are loaded into
I2CxCNT, and the client’s 7-bit address and
R/W bit are loaded into I2CxTXB. A write to I2CxTXB will cause host hardware to
automatically issue a Start condition once the bus is Idle (BFRE = 1
). Software writes to the
Start bit are ignored.1
), I2CxCNT is
nonzero (I2CxCNT != 0
), and the Clock Stretching Disable (CSD) bit is clear (CSD = 0
):0
), host
hardware issues a Stop condition, or sets MDR if the Restart Enable (RSEN) bit is set and waits for software to set the
Start bit to issue a Restart condition. CNTIF is set. 1
), host
hardware issues a Stop condition, or sets MDR if RSEN is set and waits for software to load I2CxTXB with a new client address. CNTIF is set.1
), I2CxCNT is
nonzero (I2CxCNT != 0
), and CSD is clear (CSD = 0
):