I3CxBTO

I3CxBTO

Bus Time-out Threshold

Note: The value of this register is determined as the number of I3CxCLK clocks corresponding to a desired bus time-out duration (of at least 32 times the SCL period). An internal counter incremented by the I3CxCLK clock is compared against this value to determine when a Bus Time-out occurs. Refer to section Bus Time-Out Reset for details.
0x093, 0x0C4 16     1index x

I3CxBTO

Bit  15 14 13 12 11 10 9 8  
  BTO[15:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  BTO[15:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 15:0 – BTO[15:0]: Bus Time-out Threshold

Bus Time-out Threshold