# Power Sequencing

When configured in Dual Supply mode the different voltage domains can ramp up/down independently. There are some considerations that need to be accounted for in each scenario.

Scenario #1: VDD Ramps Up Before VDDIOx

In this case, the CPU core is functional as soon as the VDD voltage level is above minimum VDD level. The VDDIOx domain is held in reset and all the MVIO pins on the corresponding VDDIOx domain remain tri-stated until the VDDIOx voltage level is above the minimum value. When the VDDIOx voltage level rises above the minimum value, the corresponding PORVDDIOx bit is set in PCON1 register.

Scenario #2: VDDIOx Ramps Up Before VDD

In this case, the corresponding VDDIOx domain becomes active, but the CPU core remains non-functional till the VDD voltage rises above minimum VDD level. Until then, the MVIO pins on the corresponding VDDIOx domain will remain tri-stated. When the VDDIOx voltage level rises above the minimum value, the corresponding PORVDDIOx bit is set in PCON1 register.

Scenario #3: VDD Loses and Regains Power While VDDIOx is Stable

In this case, when the VDD voltage level drops below the Brown-out Reset (BOR) range and if the BOR circuit is enabled, the device will undergo a full reset and will continue to stay in reset until the voltage level is above the configured BOR level. If the BOR circuit is not enabled, then the device will be functional until the voltage level drops below the minimum VDD level. This will cause a POR event. Refer to the “Resets” chapter for more information about device POR and BOR on VDD domain.

Regardless of a BOR/POR event, all the port pins (including MVIO pins) on all the voltage domains will tri-state and need to be reinitialized after the device recovers.

Scenario #4: VDDIOx Loses and Regains Power While VDD is Stable

In this case, when the VDDIOx voltage drops below the minimum value (1.62V nominal), it triggers a POR on the corresponding VDDIOx domain and the pins on this domain are tri-stated. When the VDDIOx voltage regains power and is above the corresponding domain's POR level, the POR will disengage and the pins will reload their configuration based on the PORT register settings. When the VDDIOx voltage level rises above the minimum value, the corresponding PORVDDIOx bit is set in PCON1 register.
Important: To automatically activate the I3C Low-Voltage buffers when the VDDIOx voltage drops below 1.62V (down to 1V), the user firmware must enable the bandgap reference (enable FVR module i.e. FVRCONbits.EN = 1). This enables I3C communication at voltages below 1.62V. All VDDIOx monitors are disabled below 1.62V. If the VDDIOx supply voltage drops below 1V, the corresponding MVIO pins will tri-state. When the VDDIOx supply voltage is above 1.62V the I3C Low Voltage buffers are turned off automatically.