Power Sequencing

When configured in Dual Supply mode the different voltage domains can ramp up/down independently. There are some considerations that need to be accounted for in each scenario.

Scenario #1: V_DD Ramps Up Before V_DDIOx

In this case, the CPU core is functional as soon as the V_DD voltage level is above minimum V_DD level. The V_DDIOx domain is held in reset and all the MVIO pins on the corresponding V_DDIOx domain remain tri-stated until the V_DDIOx voltage level is above the minimum value. When the V_DDIOx voltage level rises above the minimum value, the corresponding PORVDDIOx bit is set in PCON1 register.

Scenario #2: V_DDIOx Ramps Up Before V_DD

In this case, the corresponding V_DDIOx domain becomes active, but the CPU core remains non-functional till the V_DD voltage rises above minimum V_DD level. Until then, the MVIO pins on the corresponding V_DDIOx domain will remain tri-stated. When the V_DDIOx voltage level rises above the minimum value, the corresponding PORVDDIOx bit is set in PCON1 register.

Scenario #3: V_DD Loses and Regains Power While V_DDIOx is Stable

In this case, when the V_DD voltage level drops below the Brown-out Reset (BOR) range and if the BOR circuit is enabled, the device will undergo a full reset and will continue to stay in reset until the voltage level is above the configured BOR level. If the BOR circuit is not enabled, then the device will be functional until the voltage level drops below the minimum V_DD level. This will cause a POR event. Refer to the “Resets” chapter for more information about device POR and BOR on V_DD domain.

Regardless of a BOR/POR event, all the port pins (including MVIO pins) on all the voltage domains will tri-state and need to be reinitialized after the device recovers.

Scenario #4: V_DDIOx Loses and Regains Power While V_DD is Stable

In this case, when the V_DDIOx voltage drops below the minimum value (1.62V nominal), it triggers a POR on the corresponding V_DDIOx domain and the pins on this domain are tri-stated. When the V_DDIOx voltage regains power and is above the corresponding domain's POR level, the POR will disengage and the pins will reload their configuration based on the PORT register settings. When the V_DDIOx voltage level rises above the minimum value, the corresponding PORVDDIOx bit is set in PCON1 register.

Important: To automatically activate the I3C Low-Voltage buffers when the V_DDIOx voltage drops below 1.62V (down to 1V), the user firmware must enable the bandgap reference (enable FVR module i.e. FVRCONbits.EN = 1). This enables I3C communication at voltages below 1.62V. All V_DDIOx monitors are disabled below 1.62V. If the V_DDIOx supply voltage drops below 1V, the corresponding MVIO pins will tri-state. When the V_DDIOx supply voltage is above 1.62V the I3C Low Voltage buffers are turned off automatically.