PIR2

PIR2

Peripheral Interrupt Request Register 2
Note:
  1. 1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
0x46B 8  
Parent topic: Register Definitions: Interrupt Control

PIR2

Bit  7 6 5 4 3 2 1 0  
  ACTIF SCANIF CRCIF NVMIF DMA4AIF DMA4ORIF DMA4DCNTIF DMA4SCNTIF  
Access  R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS  
Reset  0 0 0 0 0 0 0 0  

Bit 7 – ACTIF: Active Clock Tuning Interrupt Flag

Active Clock Tuning Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 6 – SCANIF: Memory Scanner Interrupt Flag

Memory Scanner Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 5 – CRCIF: CRC Interrupt Flag

CRC Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 4 – NVMIF: NVM Interrupt Flag

NVM Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 3 – DMA4AIF: DMA4 Abort Interrupt Flag

DMA4 Abort Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 2 – DMA4ORIF: DMA4 Overrun Interrupt Flag

DMA4 Overrun Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 1 – DMA4DCNTIF: DMA4 Destination Count Interrupt Flag

DMA4 Destination Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 0 – DMA4SCNTIF: DMA4 Source Count Interrupt Flag

DMA4 Source Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred