I3CxBIDL

I3CxBIDL

Bus Idle Condition Threshold

Note: The value of this register is determined as the number of I3CxCLK clocks corresponding to a 200 μs Bus Idle Condition. An internal counter incremented by the I3CxCLK clock is compared against this value to determine when a Bus Idle Condition occurs. Refer to section Bus Idle Condition for details.
0x090, 0x0C1 16     1index x

I3CxBIDL

Bit  15 14 13 12 11 10 9 8  
  BIDL[15:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  BIDL[15:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 15:0 – BIDL[15:0]: Bus Idle Condition Threshold

Bus Idle Condition Threshold