INLVLx

INLVLx

Input Level Control Register
Important:
  • Refer to the “Pin Allocation Table” for details about pin availability per port
  • Unimplemented bits will read back as ‘0
    8  

INLVLx

Bit  7 6 5 4 3 2 1 0  
  INLVLx7 INLVLx6 INLVLx5 INLVLx4 INLVLx3 INLVLx2 INLVLx1 INLVLx0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  1 1 1 1 1 1 1 1  

Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLxn: Input Level Select on RX Pin

Input Level Select on RX Pin

ValueDescription
1 ST input used for port reads and interrupt-on-change
0 TTL input used for port reads and interrupt-on-change