CWGxSTR

CWGxSTR

CWG Steering Control Register(1)

Notes:
  1. 1.The bits in this register apply only when MODE = ‘b00x (CWGxCON0, Steering modes).
  2. 2.This bit is double-buffered when MODE = ‘b001.
  0x01A1 8   1 1 x

CWGxSTR

Bit  7 6 5 4 3 2 1 0  
  OVRD OVRC OVRB OVRA STRD STRC STRB STRA  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 4, 5, 6, 7 – OVRy: Steering Data OVR'y'

Steering Data OVR'y'

ValueNameDescription
x STRy = 1 CWGx'y' output has the CWG data input waveform with polarity control from POLy bit
1 STRy = 0 and POLy = x CWGx'y' output is high
0 STRy = 0 and POLy = x CWGx'y' output is low

Bits 0, 1, 2, 3 – STRy: STR'y' Steering Enable(2)

STR'y' Steering Enable(2)

ValueDescription
1 CWGx'y' output has the CWG data input waveform with polarity control from the POLy bit
0 CWGx'y' output is assigned to value of the OVRy bit