DDR2 memories support bit swapping, a technique the designer can use to interchange data lines with one another, provided that they correspond to the same byte lane (for example, any bits inside the D[0..7] lane). This is very useful when trying to optimize a DDR layout routing. The SAMA7G54 BGA343 MPU pinout is specifically optimized to match the pinout of DDR3L memory devices, therefore bit or byte swapping may not be needed for DDR3L, but useful for DDR2. LPDDR2 and LPDDR3 devices do not support bit and byte swapping.
The following figure shows an example of the bit swapping technique which can be implemented in a SAMA7G54 board design.
Byte swapping is another technique that can be used on DDR2 memories. It allows the designer to swap the data lanes with one another, also for the purpose of optimizing the layout. Remember to also swap the DQMx and DQSx signals corresponding to the swapped byte lanes, as illustrated below.
