SPI Slave Programming Interface

In addition to the standard SPI signals, RT PolarFire FPGA provide two pins—SPI_EN and IO_CFG_INTF—for configuring the SPI controller.

The following table lists the system controller’s SPI pins and specifies what must be done if a pin is not in use (unused condition). For information about unused conditions and power sequence, see UG0726: PolarFire FPGA Board Design User Guide.

Table 1. System Controller SPI Pins
SPI Pin Name Direction Description Unused Condition
SCK Bidirectional SPI clock.1 Connect to VSS through a 10 kΩ resistor
SS2 Bidirectional SPI slave select.1 Connect to VSS through a 10 kΩ resistor
SDI Input SDI input.1 Connect to VDDI3 through a 10 kΩ resistor
SDO Output SDO output.1 DNC
SPI_EN Input SPI enable.

0: SPI output tristated

1: Enabled

Pulled up or down through a resistor or driven dynamically from an external source to enable or tristate the SPI I/O.

 Connect to VSS through a 10 kΩ resistor
IO_CFG_INTF Input SPI I/O configuration.

0: SPI slave interface
1: SPI master interface

Pulled up or down through a resistor.

 Connect to VSS through a 10 kΩ resistor
1. Shared between the system controller and the FPGA fabric. When the system controller’s SPI is enabled and configured as master, the system controller hands over the control of the SPI to the fabric (after device power-up). When the SPI_EN pin is disabled (driven low) or when the SS is driven HIGH, the system controller’s SPI outputs are tristated.

2. The system controller SS pin is an active-low signal. In unused condition, the pin must be tied to VSS to avoid a floating pin on the device.

  

The SPI_EN and IO_CFG_INTF pins must be configured external to the device. This can be done by using jumpers on the board or by bootstrapping. The following table lists the SPI_EN and IO_CFG_INTF configuration for SPI slave programming.

Table 2. System Controller’s SPI Configuration - SPI Slave
SPI Pins SPI Slave Programming Description
SPI_EN IO_CFG_INTF
0 x No Dynamic switching from Slave to Master or vice-versa is not allowed. A power-cycle or device reset (DEVRST_N) is required to change the SPI configuration from Slave to Master or vice-versa by configuring the IO_CFG_INTF pin.
1 0 (SPI slave mode) Yes
1 1 (SPI master mode) No
Parent topic: SPI Slave Programming