RT PolarFire FPGA can be programmed using an external SPI master such as an external microprocessor or a FlashPro programmer through the SPI interface. See Table 2 for the pin settings that must be used to configure the system controller SPI in slave mode.
The SPI slave or master mode is determined by IO_CFG_INTF SPI pin at device Power-on Reset (POR) and cannot be switched dynamically. A power cycle or DEVRST is required to change the SPI configuration from Slave to Master or vice-versa by configuring the IO_CFG_INTF pin, as mentioned in Table 1.
When SPI is in Slave mode, fabric has no access to SPI and the SPI interface is dedicated to the system controller.
Design initialization from an external SPI flash is not supported when the device is in SPI slave programming mode. For information about design initialization, see PolarFire FPGA and PolarFire SoC FPGA Power-up and Reset User Guide.