JTAG Programming Interface

In RT PolarFire FPGA, the JTAG pins are located in a dedicated I/O Bank 3. For information about the I/O states during JTAG programming, see I/O States During Programming.

The JTAG bank voltages can be set to operate at 1.8 V, 2.5 V, or 3.3 V. The following table lists the JTAG pins.

Table 1. JTAG Pins
Pin Name Direction Weak Pull-Up/Unused Condition Description
TMS Input Yes/DNC JTAG test mode select.
TRSTB Input Yes1 JTAG test reset. Must be held low during device operation.
TDI Input Yes/DNC JTAG test data in.

In ATPG or test mode, when using a 4-bit TDI bus, this I/O is used as tdi[0].

TCK Input No2 JTAG test clock
TDO Output No/DNC JTAG test data out.
1. If TRSTB is unused and the System Controller is in suspend mode, either an external 1 kΩ pull-down resistor must be connected to it to override the weak internal pull-up or it must be driven LOW from an external source.

2. In unused condition, must be connected to VSS through 10 kΩ resistor.