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Libero IDE v9.x
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1
FlashROM, Analog System Builder, and Flash Memory System Builder
1
Introduction
1.1
FlashROM
1.2
Analog System Builder
(ASB)
1.3
Analog System Builder Peripherals
1.4
Flash Memory System Builder
1.5
Revision History
1
Microchip FPGA Support
1
Microchip Information
2
Analog System Builder, FlashROM and Flash Memory System Builder
2.1
Welcome to the
Analog System Builder
(ASB)
2.2
Analog System Builder Peripherals
2.3
Revision History
2
Microchip FPGA Support
2
Microchip Information
3
ChipEditor
3
ChipEditor (non-MVN)
3.1
Starting and exiting ChipEditor
3.2
Components of ChipEditor
3.3
Status bar
3.4
Changing an object's color
3.5
Customizing Assigned and Unassigned list boxes
3.6
Committing changes
3.7
Assigning and Unassigning logic
3.8
Moving logic to other locations
3.9
Locking logic to locations
3.10
Viewing Resources
3.11
Clusters and Super Clusters
3.12
Locating a net by name
3.13
Cross-probing between ChipEditor and Silicon Explorer
3.14
Using ChipEditor with Timer
3.15
Menus, Toolbar Buttons, and Shortcut Keys
3.16
Revision History
3
Microchip FPGA Support
3
Microchip Information
4
Designer Documentation Catalog
4.1
Designer Documentation Catalog
4.2
Revision History
4
Microchip FPGA Support
4
Microchip Information
5
Libero IDE
5.1
What's New in Libero IDE v9.1
5.2
Supported Families
5.3
Project Management
5.4
Project Files
5.5
Project Options
5.6
Settings
5.7
Preferences
5.8
Project Manager Interface
5.9
Designing with Designer Block Components
5.10
Creating a Designer Block Component in Libero IDE
5.11
Creating a Designer Block Component in Designer
5.12
Instantiating a Designer Block Component in Designer
5.13
SmartDesign
5.14
Getting Started with SmartDesign
5.15
SmartDesign User Interface
5.16
Canvas View
5.17
Grid
5.18
Instance-Instance View
5.19
Schematic View
5.20
Creating a SmartDesign
5.21
Connecting Instances
5.22
Bus Interfaces
5.23
Incremental Design
5.24
Reference
5.25
Welcome to Designer
5.26
Device Selection
5.27
Design Constraints
5.28
Families Supported
5.29
Entering Constraints
5.30
Running Layout
5.31
Device Programming
5.32
Generating Programming Files
5.33
TCL Command Reference
5.34
Project Manager Tcl Commands
5.35
Reference
5.36
Dialog Boxes
5.37
Revision History
5
Microchip FPGA Support
5
Microchip Information
6
Design Constraints for Software
6.1
Design Constraints
6.2
Families Supported
6.3
Basic Concepts
6.4
I/O Attributes
6.5
I/O Attributes Editor
6.6
Entering Constraints
6.7
Using GUI Tools
6.8
Exporting Constraint Files
6.9
Constraints by Name: Timing
6.10
Constraints by Name: Physical
6.11
Constraints by Name: Netlist Optimization
6.12
Constraints by File Format - SDC Command Reference
6.13
Design Object Access Commands
6.14
About Physical Design Constraint (PDC) Files
6.15
Constraints by File Format: GCF Command Reference
6.16
I/O Standards
6.17
Revision History
6
Microchip FPGA Support
6
Microchip Information
7
Innoveda eProduct Designer Interface Guide - UNIX
7
Introduction
7.1
About this Document
7.2
Setup
7.3
Actel-Mentor Graphics Design Flow
7.4
Actel-Mentor Graphics ePd Design Considerations
7.5
Simulation Using ViewSim
7.6
Simulation Using SpeedWave
7.7
Revision History
7
Microchip FPGA Support
7
Microchip Information
8
Innoveda eProduct Designer Interface Guide – Windows
8
Introduction
8.1
About this Document
8.2
Setup
8.3
User Setup
8.4
Project Setup
8.5
Actel-Innoveda Design Flow
8.6
Actel-Innoveda Design Considerations
8.7
Simulation Using ViewSim
8.8
Simulation Using SpeedWave
8.9
Revision History
8
Microchip FPGA Support
8
Microchip Information
9
FlashPro for Software
9.1
About FlashPro®
9.2
Supported Families
9.3
FlashPro® Interface
9.4
Introductory Programming Tutorials
9.5
Advanced Tutorials
9.6
Programming Settings and Operations
9.7
Chain Programming
9.8
Chain Editing
9.9
Configuring a Programmer
9.10
Configuring Security
9.11
IGLOO and ProASIC3 Programming
9.12
SmartFusion® and Fusion (AFS) Programming
9.13
Generating Programming Files
9.14
Importing and Exporting Files
9.15
Using Hot Keys
9.16
Troubleshooting
9.17
Electronic Parameters
9.18
Electronic Specifications
9.19
Solutions to Common Issues Using Device Debug
9.20
Frequently Asked Questions
9.21
Embedded Flash Memory (NVM) Frequently Asked Questions
9.22
Device Debug User Interface
9.23
Revision History
9
Microchip FPGA Support
9
Microchip Information
10
SmartGen Cores Reference
10.1
Basic Blocks
10.2
Clock and Management
10.3
Fusion Peripherals
10.4
Memory and Controllers
10.5
Power Management
10.6
Revision History
10
Microchip FPGA Support
10
Microchip Information
11
HDL Coding Style
11
Introduction
11.1
Design Flow
11.2
Technology Independent Coding Styles
11.3
Performance Driven Coding
11.4
Technology Specific Coding Techniques
11.5
Revision History
11
Microchip FPGA Support
11
Microchip Information
12
Libero IDE Documentation Catalog
12.1
Third-Party Documentation
12.2
Fusion®, IGLOO®, and ProASIC3 Macro Library Guide
12.3
Revision History
12
Microchip FPGA Support
12
Microchip Information
13
Libero IDE
13
What's New in Libero IDE v9.1
13.1
Supported Families
13.2
Project Management
13.3
Project Files
13.4
Project Options
13.5
Settings
13.6
Preferences
13.7
Project Manager Interface
13.8
Designing with Designer Block Components
13.9
Creating a Designer Block Component in Libero IDE
13.10
Creating a Designer Block Component in Designer
13.11
Instantiating a Designer Block Component in Designer
13.12
SmartDesign
13.13
Getting Started with SmartDesign
13.14
SmartDesign User Interface
13.15
Canvas View
13.16
Grid
13.17
Instance-Instance View
13.18
Schematic View
13.19
Creating a SmartDesign
13.20
Connecting Instances
13.21
Bus Interfaces
13.22
Incremental Design
13.23
Reference
13.24
Welcome to Designer
13.25
Device Selection
13.26
Design Constraints
13.27
Families Supported
13.28
Entering Constraints
13.29
Running Layout
13.30
Device Programming
13.31
Generating Programming Files
13.32
TCL Command Reference
13.33
Project Manager Tcl Commands
13.34
Reference
13.35
Dialog Boxes
13.36
Revision History
13
Microchip FPGA Support
13
Microchip Information
14
Antifuse Macro Library Guide for Software
14.1
Introduction
14.2
List of Combinational Macros
14.3
List of Sequential Macros
14.4
List of CC Macros
14.5
List of RAM Macros
14.6
List of Input/Output Macros
14.7
Alphabetical List of Macros
14.8
Combinational/Sequential Macros
14.9
CC-Module Flip Flops
14.10
Memory Macros
14.11
I/O Macros
14.12
Carry Chain Macros
14.13
PLL Macros
14.14
RTAX-DSP Math Macro
14.15
Simulation Support for GCLR/GPSET in Axcelerator
14.16
Revision History
14
Microchip FPGA Support
14
Microchip Information
15
MultiView Navigator
15
Overview
15.1
Getting Started
15.2
Hierarchy Window
15.3
NetlistViewer
15.4
PinEditor
15.5
I/O Attribute Editor
15.6
ChipPlanner
15.7
Floorplanning
15.8
Block Ports
15.9
Viewing Resources
15.10
Using I/O Banks
15.11
Using Active Lists
15.12
Reference
15.13
Hierarchy Window
15.14
Menus, Toolbar Buttons, and Shortcut Keys
15.15
Dialog Boxes
15.16
Revision History
15
Microchip FPGA Support
15
Microchip Information
16
NetlistViewer (non-MVN)
16
Introduction
16.1
Starting NetlistViewer
16.2
Components of NetlistViewer Standalone
16.3
Navigating Through the Netlist
16.4
Selecting Objects
16.5
Highlighting Objects
16.6
Searching for Objects
16.7
Using NetlistViewer (non-MVN) with ChipEditor
16.8
Using NetlistViewer (non-MVN) with Timer
16.9
Debugging Simulation Results
16.10
Identifying paths
16.11
Viewing Buffers
16.12
Menus, Toolbar Buttons and Shortcut Keys
16.13
Revision History
16
Microchip FPGA Support
16
Microchip Information
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
17.1
Introduction
17.2
List of Combinational Macros
17.3
List of Sequential Macros
17.4
List of RAM Macros
17.5
List of Input/Output Macros
17.6
Alphabetical List of Macros
17.7
Combinational/Sequential Macros
17.8
Revision History
17
Microchip FPGA Support
17
Microchip Information
18
ProASIC and ProASIC PLUS Macro Library for Software
18
Introduction
18.1
Combinational Cells
18.2
Storage Cells
18.3
Input/Output Cells
18.4
Memory Cells
18.5
Revision History
18
Microchip FPGA Support
18
Microchip Information
19
PinEditor (non-MVN)
19
PinEditor (non-MVN)
19.1
Starting PinEditor
19.2
Components of PinEditor (non-MVN)
19.3
Package window
19.4
Colors and symbols
19.5
Assigned and Unassigned list boxes
19.6
I/O Attribute Editor window
19.7
World View window
19.8
Status bar
19.9
Assigning pins
19.10
Unassigning pins
19.11
Locking and unlocking pins
19.12
Closing and committing pin assignments
19.13
Customizing Assigned and Unassigned list boxes
19.14
Scripting commands
19.15
Assigning I/O macros
19.16
Editing multiple rows
19.17
Sorting I/O attributes
19.18
Common I/O attributes (All Families)
19.19
Setting an I/O standard
19.20
Setting the power-up state
19.21
Setting the Slew
19.22
Specifying capacitance
19.23
Specifying I/O Threshold
19.24
Setting hot swap
19.25
Specifying Loading
19.26
Menus, Toolbar Buttons, and Shortcut Keys
19.27
File menu
19.28
Edit menu
19.29
View menu
19.30
Help menu
19.31
Revision History
19
Microchip FPGA Support
19
Microchip Information
20
SmartPower
20.1
Starting SmartPower
20.2
SmartPower Interface
20.3
Calculating Power
20.4
SmartPower Tcl Commands
20.5
Revision History
20
Microchip FPGA Support
20
Microchip Information
21
SmartTime
21
Introduction
21.1
Design Flows with SmartTime
21.2
Starting and Closing SmartTime
21.3
SmartTime Components
21.4
SmartTime Constraint Scenario
21.5
Setting SmartTime Options
21.6
SmartTime Tutorial
21.7
SmartTime Constraints Editor
21.8
SmartTime Timing Analyzer
21.9
Advanced Timing Analysis
21.10
Generating Timing Reports
21.11
Timing Concepts
21.12
Dialog Boxes
21.13
Menus, Tools, and Shortcut Keys
21.14
Data Change History – SmartTime
21.15
Constraints by File Format - SDC Command Reference
21.16
Design Object Access Commands
21.17
Glossary
21.18
Revision History
21
Microchip FPGA Support
21
Microchip Information
22
Timer
22
Welcome to Timer
22.1
Timer User Interface
22.2
Summary Tab
22.3
Timer Expanded Path Window
22.4
Clocks Tab
22.5
Paths Tab
22.6
Breaks Tab
22.7
Timer Preferences
22.8
Timer Menu Commands
22.9
Timing Report Dialog Box
22.10
Determining your Clock Frequency
22.11
Adding and Removing Break Points
22.12
Setting Preferences in Timer
22.13
Path Analysis
22.14
Specifying Timing Constraints
22.15
Constraint Guidelines
22.16
Timing Results
22.17
Keyword Filters
22.18
Calculating Delays
22.19
Using Chip Planner/ChipEditor with Timer
22.20
Timer Tcl Commands
22.21
Timing Delay Constraint Definitions
22.22
Glossary of Terms
22.23
Revision History
22
Microchip FPGA Support
22
Microchip Information
23
VHDL Vital Simulation
23
Introduction
23.1
Setup
23.2
Design Flow
23.3
Generating Netlists
23.4
Simulation with ModelSim
23.5
Revision History
23
Microchip FPGA Support
23
Microchip Information
24
Verilog Simulation
24
Introduction
24.1
Setup
24.2
Design Flow
24.3
Generating Netlists
24.4
Interpreted Simulation
24.5
Simulation with ModelSim
24.6
Revision History
24
Microchip FPGA Support
24
Microchip Information
25
Technical Support
26
About Microchip
26
Microchip FPGA Support
26
Microchip Information
Rev: A
