Libero SoC v2021.2 adds information about Power Up To Functional timing (PUFT) data in
the Design Initialization Data and Memories report. To indicate the completion of
initialization of each block (PCIe, XCVR, and RAM), a signal is asserted as part of
device initialization after power-up. For example, the PCIE_INIT_DONE
signal is asserted after all the PCIe-related registers are configured. The
DEVICE_INIT_DONE signal from PF_INIT_MONITOR is
the last signal asserted.
For more details, see the PolarFire FPGA and PolarFire SoC FPGA Device Power-Up and Resets User Guide.