The figure below shows the timing diagram for the ADC when running in Single 8- or 12-bit mode with the PGA.
1
’ in
the Control A (ADCn.CTRLA) register, the PGA and the analog modules in the ADC will not
turn OFF at the end of the conversion, eliminating the initialization time when triggering
the following conversion. The PGA will stay in the Input Sampling state until a new PGA
sampling occurs.The total conversion time (tconv) for a single result, in μs, is calculated by:
A new conversion starts immediately after a result is
available in the Result (ADCn.RESULT) register if the Free-Running (FREERUN) bit is set to
‘1
’ in the Control F (ADCn.CTRLF) register. The Free-Running conversion
rate (fconv) is calculated by: