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dsPIC33CDVL256MC506 Family Data Sheet
Operating Conditions
Host dsPIC DSC Features
High-Resolution PWM
High-Speed Analog-to-Digital Converter
Analog Features
Microcontroller Features
Debug Features
Peripheral Features
LIN Transceiver Module (Based on ATA663211 Device) (dsPIC33CDVLXXXMCX06 Only)
Safety Features
MOSFET Gate Driver Module (Based on MCP8021 Device)
Functional Safety Readiness – ISO 26262/ IEC 61508/IEC 60730
dsPIC33CDVL256MC506 Product Families
Pin Diagrams
1 64-Pin 9x9mm VGQFN (8QW)
2 64-Pin 9x9mm VGQFN (8QW)
3 64-Pin 8x8mm VQFN (8PW)
4 64-Pin 8x8mm VQFN (8PW)
1 Device Overview
2 Guidelines for Getting Started with 16-Bit Digital Signal Controllers
2.1 Basic Connection Requirements
2.2 Decoupling Capacitors
2.3 Master Clear (MCLR) Pin
2.4 ICSP Pins
2.5 External Oscillator Pins
2.6 External Oscillator Layout Guidance
2.7 Oscillator Value Conditions on Device Start-up
2.8 Unused I/Os
2.9 Bulk Capacitors
3 CPU
3.1 Registers
3.2 Instruction Set
3.3 Data Space Addressing
3.4 Addressing Modes
3.5 CPU Control/Status Registers
3.6 Arithmetic Logic Unit (ALU)
3.7 DSP Engine
4 Memory Organization
4.1 Program Address Space
4.2 Data Address Space
4.3 BIST Overview
4.4 Memory Resources
4.5 Bit-Reversed Addressing
4.6 Interfacing Program and Data Memory Spaces
5 Flash Program Memory
5.1 Table Instructions and Flash Programming
5.2 RTSP Operation
5.3 Error Correcting Code (ECC)
5.4 ECC Fault Injection
5.5 Flash OTP by ICSP™ Write Inhibit
5.6 Program Flash Memory Control Registers
5.7 ECC Control Registers
6 Resets
6.1 Reset Resources
6.2 Reset Control Register
Reset Control Register
6.3 Key Resources
7 Interrupt Controller
7.1 Interrupt Vector Table
7.2 Alternate Interrupt Vector Table
7.3 Reset Sequence
7.4 Interrupt Resources
7.5 Interrupt Control and Status Registers
7.6 INTCON1 through INTCON4
7.7 Status/Control Registers
7.8 Key Resources
8 I/O Ports
8.1 Parallel I/O (PIO) Ports
8.2 Configuring Analog and Digital Port Pins
8.3 Input Change Notification (ICN)
8.4 Peripheral Pin Select (PPS)
8.5 Considerations for Peripheral Pin Selection
8.6 Input Mapping
8.7 Virtual Connections
8.8 Output Mapping
8.9 Mapping Limitations
8.10 I/O Helpful Tips
8.11 I/O Ports Resources
9 Oscillator with High-Frequency PLL
9.1 Primary PLL
9.2 CPU Clocking
9.3 Primary Oscillator (POSC)
9.4 Internal Fast RC (FRC) Oscillator
9.5 Low-Power RC (LPRC) Oscillator
9.6 Internal Backup Fast RC (BFRC) Oscillator
9.7 Reference Clock Output
9.8 Oscillator Configuration
9.9 OSCCON Unlock Sequence
9.10 Oscillator Control Registers
10 Direct Memory Access (DMA) Controller
10.1 Summary of DMA Operations
10.2 Typical Setup
11 Controller Area Network Flexible Data-Rate (CAN FD) Modules
11.1 Features
11.2 CAN Control/Status Registers
12 High-Speed PWM
12.1 Features
12.2 Architecture Overview
12.3 Lock and Write Restrictions
12.4 PWM4H/L Output on Peripheral Pin Select
12.5 PWM Control/Status Registers
12.6 Control Registers
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13 MOSFET Gate Driver Module
13.1 Communications Port (DE2 Interconnect)
13.2 Low-Side PWM Inputs (PWMAL, PWMBL, PWMCL)
13.3 High-Side PWM Inputs (PWMAH, PWMBH, PWMCH)
13.4 Output Enable (OE) Input
13.5 Fault Output (FAULT)
13.6 Wake Input (WAKE)
13.7 Motor Phase Inputs (PHA, PHB, PHC)
13.8 High-Side N-MOSFET Gate Driver Outputs (HSA, HSB, HSC)
13.9 Bootstrap Inputs (VBA, VBB, VBC)
13.10 Low-Side N-MOSFET Gate Driver Outputs (LSA, LSB, LSC)
13.11 Bootstrap Supply (VBOOT)
13.12 +3.3V (VREG)
13.13 Power Supply Input (HVDD)
13.14 Charge Pump Flying Capacitor (CAP1, CAP2)
13.15 State Diagram
13.16 Bias Generator
13.17 Supervisor
13.18 Output Enable (OE)
13.19 Faults
13.20 Motor Control Unit
13.21 Motor Control
13.22 DE2 Communication Port
13.23 MOSFET Gate Driver Registers
13.24 Application Information
13.25 Device Protection
14 High-Speed, 12-Bit Analog-to-Digital Converter
14.1 ADC Features Overview
14.2 Analog-to-Digital Converter Resources
14.3 ADC Control Registers
15 High-Speed Analog Comparator with Slope Compensation DAC
15.1 Overview
15.2 Features Overview
15.3 DAC Control Registers
15.4 DAC Control Registers
16 Quadrature Encoder Interface (QEI)
16.1 QEI Control/Status Registers
17 Universal Asynchronous Receiver Transmitter (UART)
17.1 Architectural Overview
17.2 Character Frame
17.3 Data Buffers
17.4 Protocol Extensions
17.5 UART Control/Status Registers
18 LIN Transceiver Module
18.1 Pin Description
18.2 Functional Description
18.3 Wake-up Scenarios from Sleep Mode
18.4 Behavior Under Low Supply Voltage Condition
18.5 Application Circuit
19 Serial Peripheral Interface (SPI)
19.1 SPI Control/Status Registers
20 Inter-Integrated Circuit (I2C)
20.1 Communicating as a Host in a Single Host Environment
20.2 Setting Baud Rate When Operating as a Bus Main
20.3 Secondary Address Masking
20.4 SMBus Support
20.5 I2C Control/Status Registers
21 Single-Edge Nibble Transmission (SENT)
21.1 Transmit Mode
21.2 Receive Mode
21.3 SENT Control/Status Registers
22 Timer1
22.1 Timer1 Control Registers
23 Capture/Compare/PWM/Timer Modules (SCCP)
23.1 Time Base Generator
23.2 General Purpose Timer
23.3 Output Compare Mode
23.4 Input Capture Mode
23.5 Auxiliary Output
23.6 SCCP Control/Status Registers
24 Configurable Logic Cell (CLC)
24.1 Control Registers
24.2 CLC Control Registers
25 Peripheral Trigger Generator (PTG)
25.1 Features
25.2 PTG Registers
25.3 PTG Step Commands
26 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
26.1 CRC Control Registers
27 Current Bias Generator (CBG)
27.1 Current Bias Generator Control Registers
28 Operational Amplifier
28.1 Operational Amplifier Control Registers
29 Deadman Timer (DMT)
29.1 Deadman Timer Control/Status Registers
30 Power-Saving Features
30.1 Clock Frequency and Clock Switching
30.2 Instruction-Based Power-Saving Modes
30.3 Interrupts Coincident with Power Save Instructions
30.4 Doze Mode
30.5 Peripheral Module Disable
30.6 Power-Saving Control Registers
30.7 Power-Saving Resources
31 Special Features
31.1 Configuration Bits
31.2 Configuration Registers
31.3 Device Calibration and Identification
31.4 User OTP Memory
31.5 On-Chip Voltage Regulator
31.6 Brown-out Reset (BOR)
31.7 Dual Watchdog Timer (WDT)
31.8 JTAG Interface
31.9 In-Circuit Serial Programming™ (ICSP™)
31.10 In-Circuit Debugger
31.11 Code Protection and CodeGuard™ Security
32 Instruction Set Summary
33 Development Support
34 Electrical Characteristics
34.1 DC Characteristics
34.2 AC Characteristics and Timing Parameters
35 High-Temperature Electrical Characteristics
35.1 DC Characteristics
36 MOSFET Gate Driver Electrical Characteristics
37 LIN Transceiver Electrical Characteristics
38 Packaging Information
38.1 Package Marking Information
38.2 Package Details
39 Revision History
40 Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature

DS70005628A

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