Phase-Locked Loop (PLL)

The PLL can be used to increase the frequency of the clock source defined by the SOURCE bit in the PLL Control A (CLKCTRL.PLLCTRLA) register. The minimum input frequency of the PLL is 16 MHz, and the maximum output frequency is 48 MHz.

Initialization:
  1. 1.Enable the clock source to be used as input.
  2. 2.Configure SOURCE in CLKCTRL.PLLCTRLA to the desired clock source.
  3. 3.Enable the PLL by writing the desired multiplication factor to the Frequency Select (MULFAC) bit field in PLLCTRLA.
  4. 4.Wait for the PLL Status (PLLS) bit in the Main Clock Status (CLKCTRL.MCLKSTATUS) register to become ‘1’, indicating that the PLL has locked in on the desired frequency.

For available connections, refer to the Block Diagram figure in the CLKCTRL - Clock Controller section.