Control Register F Clear

Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.

Name:
CTRLFCLR
Offset:
0x06
Reset:
0x00
Access:
-
Bit76543210
CMP2BVCMP1BVCMP0BVPERBV
AccessR/WR/WR/WR/W
Reset0000

Bit 3 – CMP2BV: Compare 2 Buffer Valid

Compare 2 Buffer Valid

See CMP0BV.

Bit 2 – CMP1BV: Compare 1 Buffer Valid

Compare 1 Buffer Valid

See CMP0BV.

Bit 1 – CMP0BV: Compare 0 Buffer Valid

Compare 0 Buffer Valid

The CMPnBV bits are set when a new value is written to the corresponding TCAn.CMPnBUF register. These bits automatically clear on an UPDATE condition.

Bit 0 – PERBV: Period Buffer Valid

Period Buffer Valid

This bit is set when a new value is written to the TCAn.PERBUF register. This bit automatically clears on an UPDATE condition.