Power Sequencing

The system supports the following power ramp scenarios for MVIO when configured in Dual-Supply mode: When either voltage domain loses power, the MVIO I/O pins are tri-stated. If VDDIO2 regains power, the pins will reload the current configuration of the PORT registers. If VDDIO loses power, the device will reset, and the PORTs will have to be reinitialized. Refer to the Electrical Characteristics section for VDD and VDDIO2 power supply thresholds.

When a peripheral is connected to MVIO pins, it will continue operation when the pins are tri-stated. The VDDIO2S flag must be monitored to ensure the correct operation of the peripheral and I/O pins.