10BASE-T1S MAC-PHY Ethernet Controller with SPI LAN8650/1

1.1 General Terms

1.2 Buffer Types

1.3 Register Bit Types

1.4 Reference Documents

2.1 General Description

2.2 The LAN8650/1 Family

2.3 Example Systems

3 Pin Descriptions and Assignments

3.1 LAN8650 Pin Assignments

3.2 LAN8651 Pin Assignments

3.3 Pin Descriptions

3.4 Configurable DIO Pins

4 Global Functional Descriptions

4.1 Reset and Startup

4.2 Clock Manager

4.3 Interrupt Sources

4.5 Synchronization Support

4.6 Safety Features

5 Serial Peripheral Interface (SPI)

5.2 MAC Frame Data Transactions

5.3 Control Transactions

6.1 Description

6.2 Embedded Characteristics

6.3 Block Diagram

6.4 Functional Description

6.5 Programming Interface

7 Integrated PHY

7.1 Interrupt Management

7.2 Physical Layer Collision Avoidance (PLCA)

7.3 Application Controlled Media Access (ACMA)

7.4 Credit Based Traffic Shaping

7.5 Signal Quality Indicator (SQI)

7.6 Cable Fault Diagnostics

8 Application Information

8.1 SPI Connectivity

8.2 System Configuration without Sleep Mode

8.3 Power Connectivity

8.4 Electromagnetic Compatibility (EMC) Considerations

8.5 PLCA Collision Detection

8.6 Crystal Oscillator Selection

8.7 Reference Schematics

9 Operational Characteristics

9.1 Absolute Maximum Ratings

9.2 Operating Conditions

9.3 Power Consumption

9.4 Package Thermal Specifications

9.5 DC Specifications (other than 10BASE-T1S PMA)

9.6 AC Specifications

9.7 Crystal Specifications

10 Packaging Information

10.2 Package Marking Information

11 Register Descriptions

11.1 Open Alliance 10BASE-T1x MAC-PHY Standard Registers

11.2 MAC Registers

11.3 PHY PCS Registers

11.4 PHY PMA/PMD Registers

11.5 PHY Vendor Specific Registers

11.6 Miscellaneous Register Descriptions

Data Sheet Revision History

Microchip Information

The Microchip Website

Product Change Notification Service

Customer Support

Product Identification System

Microchip Devices Code Protection Feature

Quality Management System

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