The WEN signal on the generated component is connected to the write port block select input (B_BLK) for each LSRAM block according to the block depth within the component and synchronized with WCLK.
| Depth | B_BLK[2] | B_BLK[1] | B_BLK[0] |
|---|---|---|---|
| WA_MSB < N | WEN |
1 |
0 |
| WA_MSB = N | WEN |
1 |
decode( WADDR[M:M],D%2) |
| WA_MSB = M+1 | WEN | decode ( WADDR[M+1:M+1], (D/2)%2) |
decode (WADDR[M:M],D%2) |
| WA_MSB > M+1 | WEN &
decode (WADDR[WA_MSB:M+2], D/4) |
decode ( WADDR[M+1:M+1], (D/2)%2) |
decode (WADDR[M:M], D%2) |