This chapter describes an example where a Two-Port LSRAM configuration generates a component with the following address widths.
- WADDR[WA_MSB:0]
- RADDR[RA_MSB:0]
In this example, assume the following:
-
M is the width of the address on the write-port of each LSRAM block.
- N is the width of the
address on the read-port of each LSRAM block.
- The decoder logic function is
decode(addr[j:k], i), where 0 <= i <
2(j-k+1).
- D is the depth of an
LSRAM block in the array of blocks, starting at 0.
| LSRAM Block Port Depth x Width |
M, N |
| 2Kx9 |
11 |
| 1Kx18 |
10 |