The SB_CORRECT and DB_DETECT outputs are synchronized with RCLK according to the above RD latency.
The SB_CORRECT flags of each LSRAM block are gated by the block’s A_BLK signals that are pipelined one more than the RD latency value, and then OR’d together to generate the SB_CORRECT output of the component.
Similarly, the DB_DETECT flags of each LSRAM block are gated by the block’s A_BLK signals that are pipelined one more than the RD latency value, and then OR’d together to generate the DB_DETECT output of the component. As a result, both the outputs are zero whenever REN is de-asserted.