When there is no depth cascading, de-asserting REN holds the previous Read data (RD). When there is depth cascading, de-asserting REN generates zeros on RD. These different behaviors occur because the component's REN input is used to drive either the LSRAM block's A_REN input or the read-port block select input (A_BLK), depending on the cascading configuration.
Asserting REN reads the RAM at the read address RADDR onto the input of the RD register on the next rising edge of RCLK.
The default configuration for REN is unchecked, which ties the signal to the active state and removes it from the generated macro. Click the check box to insert that signal on the generated macro. Click the signal arrow (when available) to toggle its polarity.