Using the RTG4 Two-Port Large SRAM
This chapter describes the RTG4 Two-Port Large SRAM functions.
Optimization for High Speed or Low Power
Write Depth/Width and Read Depth/Width
Single Clock (CLK) or Independent Write and Read Clocks (WCLK, RCLK)
Write Enable (WEN)
Read Enable (REN)
Pipeline for Read Data Output
Register Enable (RD_EN)
Synchronous Reset (RD_SRST_N)
Asynchronous Reset (ARST_N)
Expose Write Byte Enables (WBYTE_EN)
Error Correction Code (ECC)
RD Register Truth Table