Write Leveling Training Fail

Possible Reason
Signal integrity issues on CA or DQ lines. When the Write Leveling training fails, a dialog box appears as shown in the following figure.
Figure 1. Write Leveling Training Fail
Graphical user interface, text, application Description automatically generated
Configure any one of the following parameters to a different value using the MSS Configurator when the Write Leveling training fails:
  • Memory CA ODT
  • FPGA ADD/CMD Drive
  • FPGA Vref data (as % of bank vddi)
The following figure shows the configuration of CA ODT in the DDR Memory Initialization tab.
Figure 1. Configuring CA ODT—DDR Memory Initialization Tab
Graphical user interface, application Description automatically generated
The following figure shows the configuration of ADD/CMD drive or Vref data in the DDR Controller tab.
Figure 2. Configuring ADD/CMD Drive or Vref Data—DDR Controller Tab