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PIC16F17126/46 Full-Featured 14/20-Pin Microcontrollers
Introduction
PIC16F171 Family Summary
Core Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
Block Diagram
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC16F171 Microcontrollers
4.1 Basic Connection Requirements
4.2 Power Supply Pins
4.3 Master Clear (MCLR) Pin
4.4 In-Circuit Serial Programming™ (ICSP™) Pins
4.5 Unused I/Os
5 Register and Bit Naming Conventions
5.1 Register Names
5.2 Bit Names
5.3 Register and Bit Naming Exceptions
6 Register Legend
7 Enhanced Mid-Range CPU
7.1 Automatic Interrupt Context Saving
7.2 16-Level Stack with Overflow and Underflow
7.3 File Select Registers
7.4 Instruction Set
8 Device Configuration
8.1 Configuration Words
8.2 Code Protection
8.3 Write Protection
8.4 User ID
8.5 Device ID and Revision ID
8.6 Register Definitions: Configuration Settings
8.7 Register Definitions: Device ID and Revision ID
9 Memory Organization
9.1 Program Memory Organization
9.2 Data Memory Organization
9.3 STATUS Register
9.4 PCL and PCLATH
9.5 Stack
9.6 Indirect Addressing
9.7 Register Definitions: Memory Organization
9.8 Register Summary - Memory Organization
10 Resets
10.1 Power-on Reset (POR)
10.2 Brown-out Reset (BOR)
10.3 Low-Power Brown-out Reset (LPBOR)
10.4 MCLR Reset
10.5 Windowed Watchdog Timer (WWDT) Reset
10.6 Watchdog Timer (WDT) Reset
10.7 RESET Instruction
10.8 Stack Overflow/Underflow Reset
10.9 Power-Up Timer (PWRT)
10.10 Start-Up Sequence
10.11 Memory Execution Violation
10.12 Determining the Cause of a Reset
10.13 Power Control (PCONx) Register
10.14 Register Definitions: Power Control
10.15 Register Summary - Power Control
11 OSC - Oscillator Module (With Fail-Safe Clock Monitor)
11.1 Clock Source Types
11.2 Clock Switching
11.3 Fail-Safe Clock Monitor (FSCM)
11.4 Active Clock Tuning (ACT)
11.5 Register Definitions: Oscillator Module
11.6 Register Summary - Oscillator Module
12 INT - Interrupts
12.1 Overview
12.2 INTCON Register
12.3 PIE Registers
12.4 PIR Registers
12.5 Operation
12.6 Interrupt Latency
12.7 Interrupts During Sleep
12.8 INT Pin
12.9 Automatic Context Saving
12.10 Register Definitions: Interrupt Control
12.11 Register Summary - Interrupt Control
13 Power-Saving Modes
13.1 Doze Mode
13.2 Sleep Mode
13.3 Idle Mode
13.4 Peripheral Operation in Power-Saving Modes
13.5 Register Definitions: Power-Savings Control
13.6 Register Summary - Power-Savings Control
14 WWDT - Windowed Watchdog Timer
14.1 Independent Clock Source
14.2 WWDT Operating Modes
14.3 Time-Out Period
14.4 Watchdog Window
14.5 Clearing the Watchdog Timer
14.6 Operation During Sleep
14.7 Register Definitions: Windowed Watchdog Timer Control
14.8 Register Summary - WDT Control
15 NVM - Nonvolatile Memory Control
15.1 Program Flash Memory (PFM)
15.2 Data Flash Memory (DFM)
15.3 Register Definitions: Nonvolatile Memory Control
15.4 Register Summary - NVM Control
16 I/O Ports
16.1 Overview
16.2 PORTx - Data Register
16.3 LATx - Output Latch
16.4 TRISx - Direction Control
16.5 ANSELx - Analog Control
16.6 WPUx - Weak Pull-Up Control
16.7 INLVLx - Input Threshold Control
16.8 SLRCONx - Slew Rate Control
16.9 ODCONx - Open-Drain Control
16.10 Edge Selectable Interrupt-on-Change
16.11 I2C Pad Control
16.12 I/O Priorities
16.13 MCLR/VPP/RA3 Pin
16.14 Register Definitions: Port Control
16.15 Register Summary - I/O Ports
17 IOC - Interrupt-on-Change
17.1 Overview
17.2 Enabling the Module
17.3 Individual Pin Configuration
17.4 Interrupt Flags
17.5 Clearing Interrupt Flags
17.6 Operation in Sleep
17.7 Register Definitions: Interrupt-on-Change Control
17.8 Register Summary - Interrupt-on-Change
18 PPS - Peripheral Pin Select Module
18.1 Overview
18.2 PPS Inputs
18.3 PPS Outputs
18.4 Bidirectional Pins
18.5 PPS Lock
18.6 Operation During Sleep
18.7 Effects of a Reset
18.8 Register Definitions: Peripheral Pin Select (PPS)
18.9 Register Summary - Peripheral Pin Select Module
19 CRC - Cyclic Redundancy Check Module with Memory Scanner
19.1 Module Overview
19.2 Polynomial Implementation
19.3 Data Sources
19.4 CRC Check Value
19.5 CRC Interrupt
19.6 Configuring the CRC Module
19.7 Scanner Module Overview
19.8 Scanning Modes
19.9 Configuring the Scanner
19.10 Scanner Interrupts
19.11 WWDT Interaction
19.12 Operation During Sleep
19.13 Peripheral Module Disable
19.14 Register Definitions: CRC and Scanner Control
19.15 Register Summary - CRC
20 PMD - Peripheral Module Disable
20.1 Overview
20.2 Disabling a Module
20.3 Enabling a Module
20.4 Register Definitions: Peripheral Module Disable
20.5 Register Summary - PMD
21 CLKREF - Reference Clock Output Module
21.1 Clock Source
21.2 Programmable Clock Divider
21.3 Selectable Duty Cycle
21.4 Operation in Sleep Mode
21.5 Register Definitions: Reference Clock
21.6 Register Summary - Reference CLK
22 TMR0 - Timer0 Module
22.1 Timer0 Operation
22.2 Clock Selection
22.3 Timer0 Output and Interrupt
22.4 Operation During Sleep
22.5 Register Definitions: Timer0 Control
22.6 Register Summary - Timer0
23 TMR1 - Timer1 Module with Gate Control
23.1 Timer1 Operation
23.2 Clock Source Selection
23.3 Timer1 Prescaler
23.4 Secondary Oscillator
23.5 Timer1 Operation in Asynchronous Counter Mode
23.6 Timer1 16-Bit Read/Write Mode
23.7 Timer1 Gate
23.8 Timer1 Interrupt
23.9 Timer1 Operation During Sleep
23.10 CCP Capture/Compare Time Base
23.11 CCP Special Event Trigger
23.12 Peripheral Module Disable
23.13 Register Definitions: Timer1 Control
23.14 Register Summary - Timer1
24 TMR2 - Timer2 Module
24.1 Timer2 Operation
24.2 Timer2 Output
24.3 External Reset Sources
24.4 Timer2 Interrupt
24.5 PSYNC Bit
24.6 CSYNC Bit
24.7 Operating Modes
24.8 Operation Examples
24.9 Timer2 Operation During Sleep
24.10 Register Definitions: Timer2 Control
24.11 Register Summary - Timer2
25 NCO - Numerically Controlled Oscillator Module
25.1 NCO Operation
25.2 Fixed Duty Cycle Mode
25.3 Pulse Frequency Mode
25.4 Output Polarity Control
25.5 Interrupts
25.6 Effects of a Reset
25.7 Operation in Sleep
25.8 Register Definitions: NCO
25.9 Register Summary - NCO
26 CWG - Complementary Waveform Generator Module
26.1 Fundamental Operation
26.2 Operating Modes
26.3 Clock Source
26.4 Selectable Input Sources
26.5 Output Control
26.6 Dead-Band Control
26.7 Rising Edge and Reverse Dead Band
26.8 Falling Edge and Forward Dead Band
26.9 Dead-Band Jitter
26.10 Auto-Shutdown
26.11 Auto-Shutdown Restart
26.12 Operation During Sleep
26.13 Configuring the CWG
26.14 Register Definitions: CWG Control
26.15 Register Summary - CWG
27 CCP - Capture/Compare/PWM Module
27.1 CCP Module Configuration
27.2 Capture Mode
27.3 Compare Mode
27.4 PWM Overview
27.5 Register Definitions: CCP Control
27.6 Register Summary - CCP Control
28 Capture, Compare, and PWM Timers Selection
28.1 Register Definitions: Capture, Compare, and PWM Timers Selection
28.2 Register Summary - Capture, Compare, and PWM Timers Selection
29 PWM - Pulse-Width Modulator with Compare
29.1 Output Slices
29.2 Period Timer
29.3 Clock Sources
29.4 External Period Resets
29.5 Buffered Period and Parameter Registers
29.6 Synchronizing Multiple PWMs
29.7 Interrupts
29.8 Operation During Sleep
29.9 Register Definitions: PWM Control
29.10 Register Summary - PWM
30 CLC - Configurable Logic Cell
30.1 CLC Setup
30.2 CLC Interrupts
30.3 Effects of a Reset
30.4 Output Mirror Copies
30.5 Operation During Sleep
30.6 CLC Setup Steps
30.7 Register Overlay
30.8 Register Definitions: Configurable Logic Cell
30.9 Register Summary - CLC Control
31 MSSP - Host Synchronous Serial Port Module
31.1 SPI Mode Overview
31.2 I2C Mode Overview
31.3 Baud Rate Generator
31.4 Register Definitions: MSSP Control
31.5 Register Summary - MSSP Control
32 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
32.1 EUSART Asynchronous Mode
32.2 Clock Accuracy with Asynchronous Operation
32.3 EUSART Baud Rate Generator (BRG)
32.4 EUSART Synchronous Mode
32.5 EUSART Operation During Sleep
32.6 Register Definitions: EUSART Control
32.7 Register Summary - EUSART
33 ADC - Analog-to-Digital Converter with Computation Module
33.1 ADC Configuration
33.2 ADC Operation
33.3 ADC Acquisition Requirements
33.4 Computation Operation
33.5 Register Definitions: ADC Control
33.6 Register Summary - ADC
34 OPA - Operational Amplifier
34.1 OPA Module Control
34.2 Hardware Override Control
34.3 Input Offset Voltage
34.4 OPA Operation with ADC
34.5 Register Definitions: Operational Amplifier
34.6 Register Summary - Operational Amplifier
35 DAC - Digital-to-Analog Converter Module
35.1 Output Voltage Selection
35.2 Ratiometric Output Level
35.3 Buffered DAC Output Range Selection
35.4 Operation During Sleep
35.5 Effects of a Reset
35.6 Register Definitions: DAC Control
35.7 Register Summary - DAC
36 CMP - Comparator Module
36.1 Comparator Overview
36.2 Comparator Control
36.3 Comparator Hysteresis
36.4 Comparator Interrupt
36.5 Comparator Positive Input Selection
36.6 Comparator Negative Input Selection
36.7 Comparator Response Time
36.8 Analog Input Connection Considerations
36.9 Operation in Sleep Mode
36.10 ADC Auto-Trigger Source
36.11 Register Definitions: Comparator Control
36.12 Register Summary - Comparator
37 FVR - Fixed Voltage Reference
37.1 Independent Gain Amplifiers
37.2 FVR Stabilization Period
37.3 Register Definitions: FVR
37.4 Register Summary - FVR
38 Temperature Indicator Module
38.1 Module Operation
38.2 Temperature Calculation
38.3 ADC Acquisition Time
38.4 Register Definitions: Temperature Indicator
38.5 Register Summary - Temperature Indicator
39 ZCD - Zero-Cross Detection Module
39.1 External Resistor Selection
39.2 ZCD Logic Output
39.3 ZCD Logic Polarity
39.4 ZCD Interrupts
39.5 Correction for ZCPINV Offset
39.6 Handling VPEAK Variations
39.7 Operation During Sleep
39.8 Effects of a Reset
39.9 Disabling the ZCD Module
39.10 Register Definitions: ZCD Control
39.11 Register Summary - ZCD
40 Charge Pump
40.1 Manually Enabled
40.2 Automatically Enabled
40.3 Disabled
40.4 Charge Pump Oscillator
40.5 Charge Pump Threshold
40.6 Charge Pump Ready
40.7 Register Definitions: Charge Pump
40.8 Register Summary - Charge Pump
41 Instruction Set Summary
41.1 Read-Modify-Write Operations
41.2 Standard Instruction Set
42 ICSP™ - In-Circuit Serial Programming™
42.1 High-Voltage Programming Entry Mode
42.2 Low-Voltage Programming Entry Mode
42.3 Common Programming Interfaces
43 Register Summary
44 Electrical Specifications
44.1 Absolute Maximum Ratings
44.2 Standard Operating Conditions
44.3 DC Characteristics
44.4 AC Characteristics
45 DC and AC Characteristics Graphs and Tables
45.1 IDD Graphs
45.2 IPD Graphs
45.3 I/O Rise/Fall Times Graphs
45.4 VIH - VIL Graphs
45.5 VOH - VOL Graphs
45.6 Weak Pull-Up Graphs
45.7 OSC Graphs
45.8 Brown-Out Reset/Low-Power Brown-Out Reset Graphs
45.9 Power-On Reset (POR) Graphs
45.10 Power-Up Timer (PWRT) Graphs
45.11 Windowed Watchdog Timer (WWDT) Graphs
45.12 Master Clear (MCLR) Graphs
45.13 12-Bit Analog-to-Digital Converter (ADC) Graphs
45.14 8-Bit Digital-to-Analog Converter (DAC) Graphs
45.15 Operational Amplifier (OPA) Graphs
45.16 Comparator Graphs
45.17 Fixed Voltage Reference (FVR) Graphs
45.18 Temperature Indicator Graphs
45.19 Zero-Cross Detection Graphs
46 Packaging Information
46.1 Package Details
47 Appendix A: Revision History
48 Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature

DS40002343F

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