Instantiating Into Your SmartDesign
Where is the list of cores that I can instantiate into my SmartDesign?
Can I use a block that I wrote in VHDL (or Verilog) in my SmartDesign?
My HDL module has Verilog parameters or VHDL Generics declared, how can I configure those in SmartDesign?
Parent topic:
Appendix A - FAQ