My HDL module has Verilog parameters or VHDL Generics declared, how can I configure those in SmartDesign?

If your HDL module contains configurable parameters, you must create a 'core' from your HDL before using it in SmartDesign. Once your HDL module is in the Project Manager Design Hierarchy, right click and choose Create Core from HDL. You can add bus interfaces to your module if necessary. Once this is complete, you can drag your new HDL core into the SmartDesign Canvas and configure your parameters by double clicking it.