This set features a SAMA5D27/BGA289 MPU and one 4-Gbit LPDDR2-SDRAM device (Part No.:AS4C128M32MD2A-18BIN).
The layout example in the figure above features mostly data traces routed on layer 3. In the region directly below the LPDDR2 memory device, the trace clearance is lower than the specified value due to physical constraints. On inner layers the trace clearance is not as strict as on the outer layers due to lower crosstalk. Routing using vias in pads in designs featuring devices with finer pitch results in easier routing and better clearance.
Layer 5 of the test board serves as a power plane and is also used as an impedance-matching reference for the neighboring signal layers (layers 4 and 6). The highlighted region shown in the above figure powers the SDRAM device. It covers a large surface and it does not feature any splits over any high-speed signal, in order to ensure good signal integrity.
The bottom layer is illustrated in the figure above. Because of physical constraints, some traces routed to the SDRAM device have sections with reduced trace width, from 5 to 4 mils. Improvements in signal integrity on the bottom layer can be further improved by using decoupling capacitors with a 0201-sized package instead of 0402. This makes routing easier in denser designs and improves decoupling due to lower inductance.
On layer 6, the CK/CKn and DQS2/DQS2n differential signals are being routed. Having a trace width of 4 mils and 6 mils clearance between the differential traces allows for a good 100Ω impedance matching, considering the stack-up from table 3-4. Having a low dielectric height between the signal layer and the reference plane allows for narrower traces and lower clearances for differential signals, while maintaining the same impedance, which is convenient for high-density designs.