Slave Mode

In slave mode, the SPI peripheral will remain idle with the MISO line tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the DATA register, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. If SS is driven low, the slave will start to shift out data on the first SCK clock pulse. When one byte has been completely shifted, the SPI Interrupt flag (IF) in SPI.INTFLAGS is set. The slave may continue placing new data to be sent into the SPI.DATA register before reading the incoming data. The last incoming byte will be kept in the register.

When SS is driven high, the SPI logic is halted, and the SPI slave will not receive any new data. Any partially received packet in the shift register will be lost.

As the SS pin is used to signal the start and end of a transfer, it is useful for achieving packet/byte synchronization, and keeping the slave bit counter synchronized with the master clock generator.

To avoid write collisions, the SPI peripheral can be configured in buffered mode by writing a '1' to the Buffer Mode Enable bit (BUFEN) in the Control B register (SPI.CTRLB). Then, data is copied from the Transmit Register to the Shift Register only when a receive has been completed. This means that, after data is written to the Transmit Buffer, one SPI transfer must be completed before the data is copied into the shift register.