Clock Generation

The BAUD must be set to a value that results in a TWI bus clock frequency (fSCL) equal or less than 100kHz/400kHz/1MHz, dependent on the mode used by the application (Standard mode Sm/Fast mode Fm/Fast mode plus Fm+).

The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been detected.

Figure 1. SCL Timing

The SCL frequency is given by:


The TWI.MBAUD value is used to time both SCL high and SCL low which gives the following formula of SCL frequency: