Control A


Bit 7 – IBDLY: Inter-Byte Delay Enable

Inter-Byte Delay Enable

Writing a '1' to this bit enables a fixed inter-byte delay between each data byte transmitted from the UPDI when doing multi-byte LD(S). The fixed length is two IDLE characters. Before the first transmitted byte will use the regular GT delay used for direction change.

Bit 5 – PARD: Parity Disable

Parity Disable

Writing this bit to '1' will disable parity detection in the UPDI by just ignoring the Parity bit. This feature is recommended only during testing.

Bit 4 – DTD: Disable Timeout Detection

Disable Timeout Detection

Setting this bit disables the timeout detection on the PHY layer, which requests a response from the ACC layer within a specified time (65536 UPDI clock cycles).

Bit 3 – RSD: Response Signature Disable

Response Signature Disable

Writing a '1' to this bit will disable any response signatures generated by the UPDI. This is to reduce the protocol overhead to a minimum when writing large blocks of data to the NVM space. Disabling the Response Signature should be used with caution, and only when the delay experienced by the UPDI when accessing the system bus is predictable, otherwise loss of data may occur.

Bits 2:0 – GTVAL[2:0]: Guard Time Value

Guard Time Value

This bit field selects the Guard Time Value that will be used by the UPDI when the transmission mode switches from RX to TX. The Guard time is equal to the Baud Rate used in 1-Wire mode.

0x0 UPDI Guard Time: 128 cycles (default)
0x1 UPDI Guard Time: 64 cycles
0x2 UPDI Guard Time: 32 cycles
0x3 UPDI Guard Time: 16 cycles
0x4 UPDI Guard Time: 8 cycles
0x5 UPDI Guard Time: 4 cycles
0x6 UPDI Guard Time: 2 cycles
0x7 GT off (no extra Idle bits inserted)