ADC - Analog-to-Digital Converter
One Extra Measurement Performed After Disabling ADC Free-Running Mode
Pending Event Stuck When Disabling the ADC
ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD < 2.7V
ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty Cycle
Parent topic:
Silicon Errata Issues