Device-Level Anti-Tamper Features

Both the device families include a number of built-in tamper detection and response capabilities that can be used to enhance the security of the device. These countermeasures are intended to address various types of attacks that include non-invasive, semi-invasive, and invasive attacks. The System Controller can detect a number of conditions that may indicate attempted tampering with the device.

The anti-tamper system present in device includes voltage, frequency, and temperature monitors. When a tamper condition is detected, a notification event is sent to the fabric through one of many dedicated control lines. Voltages and temperature can be digitally monitored through another fabric interface. For more information, see Temperature and Voltage Sensor.

User logic, in response to the detected tamper event, can request the system controller to disable all IO pins, lock-down, reset, or zeroize the device through the tamper response interface. Ignoring the event does not impact user design operation. The tamper responses may also be initiated on-demand by the user (for example, if the user has their own system-level tamper detection connected to FPGA IOs).

The devices also incorporate DPA countermeasures for all built-in design security protocols to protect the secret keys from discovery using side-channel analysis.

See Device-Level Anti-Tamper Features for more information about anti-tamper features.