IO Disable

The I/O disable response allows the user design to immediately disable user I/Os (non-dedicated) to prevent any further communication. For FPGA I/Os, I/O disable is implemented on a per-IO basis, according to user pre-programmed per-IO configuration flash bits. The I/O disable persists for as long as the user holds IO_DISABLE asserted. During I/O disable, outputs of FPGA I/O cells are tri-stated and inputs from I/O cells to the internals of the device are specified as low. All output buffers are tri-stated (any configured pull-up or pull-down is still honored) and input buffers are disabled. Configuring FPGA I/Os to support the per-IO disable feature is controlled in the Libero I/O editor column User I/O Lock Down.

For PolarFire SoC FPGA MSS-related I/Os, the I/Os are disabled on a per-bank basis, according to user pre-programmed per-IO configuration flash bits. The IO disable persists for as long as the user holds IO_DISABLE asserted. During I/O disable, outputs of MSS related I/O cells of any bank for which lockdown is enabled, are tri-stated with weak-pull up active and inputs from I/O cells to the internals of the device are specified as low. All output buffers are tri-stated (any configured pull-up or pull-down is still honored) and input buffers are disabled. Configuring PolarFire SoC FPGA MSS I/Os to support the per-IO or per-bank disable feature is controlled in the PolarFireSoC MSS Configurator tool.

Note: The I/O disable feature does not disable transceiver I/Os. Hence, you must put the transceiver blocks in reset before asserting the IO_Disable signal to disable transceiver I/Os.