Hardware Supported Bus Time-Out Detection

The SMBus protocol requires a bus watchdog to prevent a stalled device from holding the bus indefinitely. The stand-alone I²C module provides a hardware-supported Bus Time-Out (BTO) feature to detect these bus failures. The I2C Bus Time-Out Clock Source Selection (I2CxBTOC) register provides several clock sources that can be used as the BTO time base. The I2C Bus Time-Out (I2CxBTO) register is used to determine the actual BTO time period, as well as how the module responds to a time-out event.

If either of these conditions are true, an internal time-out counter increments, and continues to increment as long as the condition stays true, or until the time-out period has expired. If these conditions change (e.g. SCL = 1), the internal time-out counter is reset by module hardware.

The Bus Time-Out Clock Source Selection (BTOC) bits select the BTO clock source. If an oscillator is selected as the time-out clock source, such as the LFINTOSC, the time-out clock base period is approximately 1 ms. If a timer is selected as the time-out clock source, the timer can be configured to produce a variety of time periods.

The Time-Out Time Selection (TOTIME) bits and the Time-Out Prescaler Extension Enable (TOBY32) bit are used to determine the BTO period. The value written into TOTIME multiplies the base time-out clock period. For example, if a value of ‘35’ is written into the TOTIME bits, and the LFINTOSC is selected as the time-out clock source, the time-out period is approximately 35 ms (35 x 1 ms). If the TOBY32 bit is set (TOBY32 = 1), the time-out period determined by the TOTIME bits is multiplied by 32. If TOBY32 is clear (TOBY32 = 0), the time-out period determined by the TOTIME bits is used as the time-out period.

The examples below illustrate possible time-out configurations.

Copyvoid Init_BTO_35(void)        // Selections produce a 35 ms BTO period
{
  I2C1BTOC = 0x06;              // LFINTOSC as BTO clock source
  I2C1BTObits.TOREC = 1;        // Reset I2C interface, set BTOIF            
  I2C1BTObits.TOBY32 = 0;       // BTO time = TOTIME * TBTOCLK        
  I2C1BTObits.TOTIME = 0x23;    // TOTIME = TBTOCLK * 35 
                                // = 1 ms * 35 = 35 ms
           
}

Copyvoid Init_BTO_64(void)    // Selections produce a 64 ms BTO period
{
  I2C1BTOC = 0x06;                // LFINTOSC as BTO clock source
  I2C1BTObits.TOREC = 1;          // Reset I2C interface, set BTOIF
  I2C1BTObits.TOBY32 = 1;         // BTO time = TOTIME * TBTOCLK * 32 
                                  // = 2 ms * 32 = 64 ms    
  I2C1BTObits.TOTIME = 0x02;      // TOTIME = TBTOCLK * 2 
                                  // = 1 ms * 2 = 2 ms
}

The Time-Out Recovery Selection (TOREC) bit determines how the module will respond to a BTO event. When a BTO event occurs and TOREC is set (TOREC = 1), the I²C module is reset, and module hardware sets the Bus Time-Out Interrupt Flag (BTOIF) bit and the generic I²C Error Interrupt Flag (I2CxEIF) bit. If the Bus Time-Out Interrupt Enable (BTOIE) bit is also set, an interrupt will be generated. If a BTO event occurs and TOREC is clear (TOREC = 0), the BTOIF and I2CxEIF bits are set but the module is not reset.

If the module is configured in Client mode with TOREC set (TOREC = 1), and a BTO event occurs (regardless of the state of the Client Mode Active (SMA) bit), the module is immediately reset, the SMA and Client Clock Stretching (CSTR) bits are cleared, and BTOIF is set.

If the module is configured in Client mode with TOREC clear (TOREC = 0), and a BTO event occurs (regardless of the state of the SMA bit), BTOIF and I2CxEIF are set but user software must reset the module.

If the module is configured in Host mode with TOREC set (TOREC = 1), and the BTO event occurs while the host is active (Host Mode Active (MMA) = 1), the Host Data Ready (MDR) bit is cleared, the module will immediately attempt to transmit a Stop condition, and sets the BTOIF and I2CxEIF bits. Stop condition generation may be delayed if a client device is stretching the clock, but will resume once the clock is released, or if the client holding the bus also has a BTO event occur. The MMA bit is only cleared after the Stop condition has been generated.

If the module is configured in Host mode with TOREC clear (TOREC = 0), and the BTO event occurs while the host is active (MMA = 1), the MDR bit is cleared and the BTOIF and I2CxEIF bits are set, but user software must initiate the Stop condition by setting the P bit.