Differences Between the MSSP and Stand-Alone I2C Modules

The stand-alone I²C module has several important differences when compared to Microchip's Host Synchronous Serial Port (MSSP) module:

Dedicated Address, Receive, and Transmit Buffers
Interrupts for Address Match, Transmit Buffer Empty, Receive Buffer Full, Bus Time-out, Data Byte Count, Acknowledge and Not Acknowledge
Clock Stretching Hardware for:
- RX buffer full
- TX buffer empty
- Address match
- Acknowledgment
Hardware Supported Bus Time-out Detection
Data Byte Counter
Programmable SDA Hold Time
Programmable Bus Free Time
Dedicated I²C Pad Control Registers
TRIS Register Setting
Serial Clock (SCL) Source and Configuration

Table 1. Comparison Between Stand-Alone I²C and MSSP Modules
Feature	I²C		MSSP
Buffers/Registers
Address Buffers	I2CxADB0	I2CxADB1	SSPxADD
	I2CxADR0	I2CxADR1
	I2CxADR2	I2CxADR3
Transmit Buffer	I2CxTXB		SSPxBUF
Receive Buffer	I2CxRXB		SSPxBUF
Byte Count	I2CxCNT, I2CxCON3		None
Bus Time-Out	I2CxBTO, I2CxBTOC		None
I²C Module Control	I2CxCON0		SSPxCON1
	I2CxCON1		SSPxCON2
	I2CxCON2		SSPxCON3
	I2CxCON3		None
I²C Interrupt Control	I2CxPIE	PIEx	PIEx
I²C Interrupt Control	I2CxPIR	PIRx	PIRx
I²C Error Control	I2CxERR		PIEx
			PIRx
			SSPxCON1
I²C Status	I2CxSTAT0	I2CxSTAT1	SSPxSTAT
I²C Status	I2CxCON1		SSPxCON2
I²C Pad Control	RxyI2C		RxyI2C⁽¹⁾
Interrupt bits
Byte Count	CNTIF, I2CxIF		None
ACK Detect	ACKTIF, I2CxIF		SSPxIF
Data Write	WRIF, RXIF, I2CxIF		SSPxIF
Address Match	ADRIF, I2CxIF		None
Start Condition	SCIF, I2CxIF		SCIF, SSPxIF
Restart Condition	RSCIF, I2CxIF		SCIF, SSPxIF
Stop Condition	PCIF, I2CxIF		PCIF, SSPxIF
Transmit Buffer Empty	TXIF, I2CxIF		SSPxIF
Receive Buffer Full	RXIF, I2CxIF		SSPxIF
Bus Time-Out	BTOIF, I2CxEIF		None
Bus Collision	BCLIF, I2CxEIF		BCLxIF, SSPxIF
NACK Detect	NACKIF, I2CxEIF		SSPxIF
Status Bits
Bus Free Indication	BFRE		None
Host Mode Active	MMA		None
Client Mode Active	SMA		None
Host Data Request	MDR		None
Acknowledge Status	ACKSTAT		ACKSTAT
Acknowledge Time Status	ACKT		ACKTIM
Receive Overflow	RXO		SSPOV
Transmit Underflow	TXU		None
Transmit Write Error	TXWE		WCOL
Transmit Buffer Empty	TXBE		BF
Receive Read Error	RXRE		None
Receive Buffer Full	RXBF		BF
Data/Address Indicator	D		D/A
Read/Write Indicator	R		R/W
Enable/Action Bits
Module Enable	EN		SSPxEN
Restart Enable	RSEN		RSEN
Initiate Start Condition	When:		SEN
	ABD = `0`: Write to I2CxTXB - Hardware sets S
	ABD = `1`: Software sets S
Initiate Restart Condition	When:		RSEN
	ABD = `0`: Write to I2CxTXB - Hardware sets S (when RSEN = `1`)
	ABD = `1`: Software sets S (when RSEN = `1`)
Initiate Stop Condition	P, Hardware		PEN
Enable Clock Stretching	CSD		SEN
Clock Stretch Release	CSTR		CKP
General Call Enable	GCEN		GCEN
Enable Acknowledge Sequence	Hardware		ACKEN
Receive Enable	EN		RCEN
Clock Source and Configuration	I2CxCLK, FME, I2CxBAUD		SSPM, SSPxADD
SDA Hold Time	SDAHT		SDAHT
Bus Free Time Configuration	BFRET		None
Bus Time-Out Configuration	I2CxBTO, I2CxBTOC		None
Byte Count Configuration	I2CxCNT, ACNT, ACNTMD		None
Address Hold Enable	ADRIE		AHEN
Data Hold Enable	WRIE		DHEN
SCL/SDA Pin Control
Weak Pull-up Control	PU<1:0> bits of RxyI2C		WPUx Register
Use of internal pull-ups on bus?	Yes		Yes⁽¹⁾
Input Threshold Control	TH<1:0> bits of RxyI2C		INLVLx Register
SMBus Threshold Control	TH<1:0> bits of RxyI2C		CKE bit of SSPxSTAT Register
Slew Rate Control	SLEW bit of RxyI2C		SMP bit of SSPxSTAT Register
Pin Direction Control	TRIS (TRIS = `0`)		TRIS (TRIS = `1`)
Open-Drain Control	ODCONx Register		Hardware Control

Note:

1.The RxyI2C register is only available on select devices that contain the MSSP module(s). For devices that do not utilize the RxyI2C registers, internal Weak Pull-up resistors are not recommended for use, and input threshold levels and slew-rate control are determined by the INVLV and SLRCON registers, respectively.