Data Byte Count

The stand-alone I²C module adds a hardware data byte count feature to specify how many data bytes are in a complete I²C packet. The data byte count does not include address bytes. The I²C Byte Count (I2CxCNT) register is used to specify the length, in bytes, of the complete transaction. The value loaded into I2CxCNT will decrement by module hardware each time a data byte is transmitted or received by the module. This differs from the MSSP module, which did not have a byte count feature.

When a byte transfer causes the I2CxCNT register to decrement to ‘0’, the Byte Count Interrupt Flag (CNTIF) bit is set, and if the Byte Count Interrupt Enable (CNTIE) is set, the general purpose I2C Interrupt Flag (I2CxIF) bit of the Peripheral Interrupt Registers (PIRx) is also set. If the I2C Interrupt Enable (I2CxIE) bit of the Peripheral Interrupt Enable (PIEx) registers is set, module hardware will generate an interrupt event. The CNTIF bit must be cleared in order to resume normal operations.

Upon the 8^th falling edge in Receive mode or the 9^th falling edge in Transmit mode of the data byte that caused the I2CxCNT to reach a zero value, the Count Interrupt Flag (CNTIF) and generic I2CxIF bits are set. The CNTIF bit must be cleared in order to resume normal operations.

The I2CxCNT register can be read at any time, but since I2CxCNT is decremented on the asynchronous SCL signal, a double read is recommended to ensure a valid count value.

The I2CxCNT register can be written to, but writing must not occur during the 8^th falling SCL edge of a reception, or during the 9^th falling SCL edge of a transmission. Writing during either of those bit times may corrupt the I2CxCNT register. In Client mode, I2CxCNT can be safely written to any time the clock is not being stretched (CSTR = 0), or after a Stop condition has been received (Stop Condition Interrupt Flag (PCIF) = 1). In Host mode, I2CxCNT can be safely written to any time the Host Data Ready (MDR) or Bus Free (BFRE) bits are set. If the I²C packet is longer than 65,536 bytes, the I2CxCNT register can be updated mid-message to prevent the count from reaching zero; however, the preventative measures listed above must be followed.

When in either Client Read or Host Write mode and the I2CxCNT value is nonzero (I2CxCNT != 0), the value of the Acknowledge Data (ACKDT) bit (0 = ACK, 1 = NACK) is used as the Acknowledgment response. When I2CxCNT reaches zero (I2CxCNT = 0), the value of the Acknowledge End of Count (ACKCNT) bit (0 = ACK, 1 = NACK) is used for the Acknowledgment response.

In Host mode, if the Restart Enable (RSEN) bit is set (RSEN = 1) and I2CxCNT = 0, the host will stretch the clock and wait for the S (Start) bit to be set (when ABD = 0) or I2CxTXB is loaded (ABD = 1) before generating a Restart condition and the transmitting the address of the next client. If both I2CxCNT = 0 and RSEN = 0, module hardware will generate a Stop condition upon the 9th falling edge of SCL.