The stand-alone I2C module contains additional interrupt features designed to assist with communication functions. In addition to the MSSP module’s Start/Restart condition (SCIF), Stop condition (PCIF), Bus Collision (BCLxIF), and transmit, receive and acknowledge (SSPxIF) interrupts, the stand-alone I2C module adds an Address Match (ADRIF), Transmit Buffer Empty (TXBE), Receive Buffer Full (RXBF), Bus Time-Out (BTOIF), Data Byte Count (CNTIF), Acknowledge Status Time (ACKTIF) and Not Acknowledge Detect (NACKIF).
The stand-alone I2C module incorporates a new register, the I2C Interrupt Flag register (I2CxPIR), which handles several I2C related interrupts. Additionally, when any of the Flag bits in I2CxPIR become set, the generic I2C Interrupt Flag (I2CxIF) is also set. It is important to note that the generic I2CxIF bit is read-only and can only be cleared when all bits in the I2CxPIR register are clear. The individual interrupts are enabled through the I2CxPIE register. If the matching Interrupt Enable bit is set, an interrupt is generated whenever the Interrupt Flag bit is set. If the appropriate Interrupt Enable bit is clear, the Interrupt Flag will still be set when the Interrupt condition occurs. However, no interrupt will be triggered.
The I2CxPIR contains the following Interrupt Flag bits:
The CNTIF bit becomes set (CNTIF = 1) when the I2CxCNT register value
reaches zero, indicating that all bytes in the data frame have been transmitted or
received. CNTIF is set after the 9th falling edge of SCL when I2CxCNT =
0. The MSSP module does not have a byte counter in hardware; byte
counts would have to be controlled through user software alone.
The ACKTIF bit becomes set (ACKTIF = 1) after the 9th falling
edge of SCL for any byte when the device is addressed as a client in any I2C
Client mode or I2C Multi-Host mode whenever an ACK
is detected. The MSSP module used the ACKSTAT bit in the SSPxCON2 register to indicate
whether an ACK was received. The ACKSTAT bit does not generate
an interrupt, so the bit must be polled to determine its state.
The WRIF bit becomes set (WRIF = 1) after the 8th falling
edge of SCL when the module receives a data byte. This bit is active in any
I2C Client mode or I2C Multi-Host mode. Once the data byte is
received, WRIF is set, as are the Receive Buffer Full (RXBF) Status bit, the
I2C Receive Interrupt Flag (I2CxRXIF) bit and the generic I2CIF bit. The
WRIF bit is read/write and must be cleared by user software, while the RXBF, I2CxRXIF
and I2CIF are read-only, and are only cleared by reading the I2CxRXB. In comparison, the
MSSP utilizes the Buffer Full (BF) bit in the SSPxSTAT register to indicate that the
SSPxBUF is full. When a byte is received, the BF and SSPxIF bits are set on the
8th falling edge of SCL.
The ADRIF bit becomes set on the 8th falling edge of SCL after the module has received either a matching 7-bit address byte or the matching upper or lower bytes of a 10-bit address. This bit is only active in Client mode or Multi-Host mode. Upon receiving a matching address byte, the ADRIF and I2CxIF bits are set. This differs from the MSSP module that uses the BF bit. When an address or data byte is received, both the BF and SSPxIF bits are set, but user software must determine whether the received byte was an address or data.
The PCIF bit is set whenever a Stop condition is detected on the bus. The PCIF bit is present in both the stand-alone and MSSP modules, and work the same way.
The RSCIF bit is set upon the detection of a Restart condition. The MSSP module used the Start Condition Interrupt Flag (SCIF) for both Start and Restart conditions.
The SCIF bit is set upon the detection of a Start condition. Both the stand-alone and MSSP modules use this bit, although the MSSP uses it to detect both Start and Restart conditions.
In addition to the I2CxPIR register, the stand-alone module incorporates the I2C Error register (I2CxERR). The I2CxERR register contains three Interrupt Flag bits that are used to detect bus errors. These bits are read/write and must be cleared by user software. The I2CxERR register also includes the Enable bits for these three functions.
The I2CxERR register contains the following Interrupt Flag bits:
The BTOIF bit is set when a bus time-out occurs. The bus time-out time frame is
controlled by the I2C Bus Time-Out (I2CxBTO) register, and if available, the
I2C Bus Time-out Clock Source Selection (I2CxBTOC) register. When a bus
time-out event occurs and the module is configured as a client and is active (SMA =
1), the BTOIF bit is set, the SMA and CSTR bits are cleared, and
the module is immediately Reset. If a bus time-out event occurs and the module is
configured as a host and is active (MMA = 1), BTOIF is set, and module
hardware immediately tries to issue a Stop condition. In either case, when BTOIF becomes
set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is also set. The
I2CxEIF bit is read-only, and is cleared by hardware when all error Interrupt Flag bits
in the I2CxERR register are clear. The MSSP module does not include a hardware-based bus
time-out feature. However, software may use an available timer to monitor for a time-out
event.
The BCLIF bit is set whenever a bus collision is detected. A bus collision occurs anytime the SDA input is sampled low while both the SDA and SCL outputs are high. When a bus collision event occurs, the BCLIF and I2CxEIF bits are set. Both the stand-alone and MSSP modules use the BCLIF to detect bus collisions.
The NACKIF is set when either the host or the client is active (SMA = 1
|| MMA = 1) and a NACK is detected on the bus. A NACK response occurs
on the 9th SCL pulse when the SDA line is released high. When the module is
in Host mode, a NACK can be issued when the host has finished receiving data from the
client, or in the event it did not receive a byte. In Client mode, the client issues a
NACK when it does not receive a matching address, or did not receive the last data byte.
A NACK may also be automatically generated by module hardware if any of the following
bits are set, which will set both the NACKIF and I2CxEIF bits: