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dsPIC33AK512MPS512 Family Data Sheet
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Operating Conditions
High-Performance dsPIC33A DSP/RISC CPU
Memory Features
Security Features
High-Speed PWM
High-Speed Analog-to-Digital Converters
Peripheral Features
Controller Features
Analog Features
Safety Features
Functional Safety Support
Qualification
Programming and Debug Interfaces
dsPIC33AK512MPS512
Family Features
Pin Diagrams
1
Pinout I/O Descriptions
2
Device Overview
3
Guidelines for Getting Started with Digital Signal Controllers
3.1
Basic Connection Requirements
3.2
Decoupling Capacitors
3.3
Power Sequencing
3.4
Buck Converter Guidelines and Considerations
3.5
Master Clear (
MCLR
) Pin
3.6
ICSP Pins
3.7
External Oscillator Pins
3.8
External Oscillator Layout Guidance
3.9
Oscillator Value Conditions on Device Start-up
3.10
Unused I/Os
3.11
Targeted Applications
4
CPU
4.1
Architectural Overview
4.2
Register Summary
4.3
Operation
4.4
Prefetch Branch Unit (PBU)
4.5
Performance Monitor Unit (PMU)
4.6
Floating-Point Unit (FPU) Coprocessor
5
Memory Organization
5.1
Device-Specific Information
5.2
Architectural Overview
5.3
Register Summary
5.4
BMX Operation
5.5
Application Example
6
Data Memory
6.1
Device-Specific Information
6.2
Architectural Overview
6.3
Register Summary
6.4
Operation
7
Flash Program Memory
7.1
Device-Specific Information
7.2
Register Summary
7.3
Operation
7.4
Flash Dual Partition
7.5
Application Example
8
Configuration Bits
8.1
Configuration Register Summary
8.2
Device Calibration and Identification
9
Security Module
9.1
Architectural Overview
9.2
Register Summary
9.3
Flash Memory Map
9.4
Device Locking
9.5
Flash Protection Regions
9.6
Cryptographic Accelerator
9.7
Peripheral Access Controller (PAC)
10
Resets
10.1
Architectural Overview
10.2
Register Summary
10.3
Operation
10.4
Application Example
10.5
Effects of Reset
11
Interrupt Controller
11.1
Device-Specific Information
11.2
Architectural Overview
11.3
Interrupt Vector Table
11.4
Register Summary
11.5
Operation
11.6
Interrupt Control and Status Registers
11.7
Priority
11.8
Interrupt Sequence
11.9
Non-Maskable Traps
11.10
Interrupt Operations
12
I/O Ports with Edge Detect
12.1
Device-Specific Information
12.2
Architectural Overview
12.3
Register Summary
12.4
Operation
12.5
Application Example
12.6
Interrupts
12.7
Power-Saving Modes
12.8
Effects of Various Resets
13
Oscillator Module
13.1
Device-Specific Information
13.2
Architectural Overview
13.3
Register Summary
13.4
Operation
14
Direct Memory Access (DMA) Controller
14.1
Device-Specific Information
14.2
Architectural Overview
14.3
Register Summary
14.4
Operation
14.5
Application Examples
14.6
Interrupts
14.7
Power-Saving Modes
15
CAN Flexible Data-Rate (FD) Protocol Module
15.1
Device-Specific Information
15.2
Features
15.3
CAN FD Message Frames
15.4
Register Summary
15.5
Modes of Operation
15.6
Configuration
15.7
Message Transmission
15.8
Transmit Event FIFO - TEF
15.9
Message Filtering
15.10
Message Reception
15.11
FIFO Behavior
15.12
Timestamping
15.13
Interrupts
15.14
Error Handling
16
High-Resolution PWM with Fine Edge Placement
16.1
Device-Specific Information
16.2
High-Resolution Mode (Fine Edge Placement)
16.3
Architectural Overview
16.4
Register Summary
16.5
Operation
16.6
Application Examples
16.7
Interrupts
16.8
Power-Saving Modes
17
40 MSPS Analog-to-Digital Converter (ADC)
17.1
Device-Specific Information
17.2
ADC Architectural Overview
17.3
Register Summary
17.4
Operation
17.5
Application Examples
18
Effects of Reset
19
Integrated Touch Controller (ITC)
19.1
Device-Specific Information
19.2
Registers
19.3
Touch Controller Operation
19.4
Application Example
20
High-Speed Analog Comparator with Slope Compensation DAC
20.1
Device-Specific Information
20.2
Architectural Overview
20.3
Register Summary
20.4
Operation
20.5
Application Examples
21
Quadrature Encoder Interface (QEI)
21.1
Device-Specific Information
21.2
Architectural Overview
21.3
Register Summary
21.4
Operation
21.5
Application Example
21.6
Interrupts
21.7
QEI Operation in Power-Saving Modes
22
Universal Asynchronous Receiver Transmitter (UART)
22.1
Device-Specific Information
22.2
Architectural Overview
22.3
Register Summary
22.4
Operation
22.5
Application Examples
22.6
Interrupts
22.7
Power-Saving Modes
23
Serial Peripheral Interface (SPI)
23.1
Device-Specific Information
23.2
Architectural Overview
23.3
Register Summary
23.4
Operation
23.5
Interrupts
23.6
Power-Saving and Debug Modes
24
Inter-Integrated Circuit (I
2
C)
24.1
Device-Specific Information
24.2
Architectural Overview
24.3
I2C System Overview
24.4
Register Summary
24.5
Operation
24.6
Application Examples
24.7
Interrupts
24.8
Operation in Power-Saving Modes
25
Single-Edge Nibble Transmission (SENT)
25.1
Device-Specific Information
25.2
Architectural Overview
25.3
Register Summary
25.4
Operation
25.5
Application Examples
25.6
Interrupts
25.7
Power-Saving Modes
25.8
Effects of a Reset
26
Bidirectional Serial Synchronous (BiSS) Module
26.1
Device-Specific Information
26.2
Architectural Overview
26.3
Register Summary
26.4
Operation
26.5
Application Examples
26.6
Interrupts
26.7
Power Saving Modes
26.8
Terminology
27
Timers
27.1
Device-Specific Information
27.2
Architectural Overview
27.3
Register Summary
27.4
Operation
27.5
Interrupts
27.6
Power-Saving Modes
27.7
Effects of Various Resets
28
Capture/Compare/PWM/Timer Modules (SCCP/MCCP)
28.1
Device-Specific Information
28.2
MCCP
28.3
Architectural Overview
28.4
Register Summary
28.5
Operation
28.6
Power-Saving Modes
28.7
Effects of a Reset
29
Configurable Logic Cell (CLC)
29.1
Device-Specific Information
29.2
Architecture
29.3
Register Summary
29.4
Operation
29.5
CLC Application Example
29.6
CLC Interrupts
29.7
Power-Saving Modes
30
Peripheral Trigger Generator (PTG)
30.1
Device-Specific Information
30.2
Architectural Overview
30.3
Register Summary
30.4
Operation
30.5
Application Examples
30.6
Interrupts
30.7
Power-Saving Modes
31
32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
31.1
Architectural Overview
31.2
Register Summary
31.3
Operation
31.4
Application Examples
31.5
Power-Saving Modes
32
Current Bias Generator (CBG)
32.1
Device-Specific Information
32.2
Architectural Overview
32.3
Current Bias Generator Control Register
Current Bias Generator Control Register
32.4
Operation
32.5
Application Examples
32.6
Interrupts
32.7
Power-Saving Modes
32.8
Effects of a Reset
33
UREF Reference Output
33.1
Device-Specific Information
33.2
UREF Control Register 1
UREF Control Register 1
34
Operational Amplifier (Op Amp)
34.1
Device-Specific Information
34.2
Architectural Overview
34.3
Op Amp Register Summary
34.4
Operations
34.5
Op Amp Application Examples
35
Watchdog Timer (WDT)
35.1
Device-Specific Information
35.2
Architectural Overview
35.3
Register Summary
35.4
Operation
35.5
Watchdog Timer Reset
35.6
Power-Saving Modes
35.7
WDT Generic Trap
35.8
WDT Sample Configuration
36
Deadman Timer (DMT)
36.1
Architectural Overview
36.2
Register Summary
36.3
Operation
37
Device Power-Saving Modes
37.1
Architectural Overview
37.2
Register Summary
37.3
Operation
38
JTAG Interface
39
In-Circuit Debugger
40
Instruction Set Summary
41
Development Support
42
Electrical Characteristics
42.1
DC Characteristics
42.2
AC Characteristics and Timing Parameters
43
Packaging Information
43.1
Package Marking Information
43.2
Package Details
44
Revision History
45
Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature
