Conversion Timing

A normal conversion takes 13 CLK_ADC cycles. The actual sample-and-hold takes place two CLK_ADC cycles after the start of a conversion. The start of conversion is initiated by writing a ‘1’ to the STCONV bit in ADCn.COMMAND register. When a conversion is complete, the result is available in the Result (ADCn.RES) register, and the Result Ready (RESRDY) interrupt flag is set in the Interrupt Flags (ADCn.INTFLAGS) register. The interrupt flag will be cleared when the result is read from the Result (ADCn.RES) register, or by writing a ‘1’ to the RESRDY bit in the ADCn.INTFLAGS register.

Figure 1. ADC Timing Diagram - Single Conversion

Both sampling time and sampling length can be adjusted using the Sample Delay (SAMPDLY) bit field in the Control D (ADCn.CTRLD) register and the Sample Length (SAMPLEN) bit field in the Sample Control (ADCn.SAMPCTRL) register. Both of these control the ADC sampling time in some CLK_ADC cycles. This allows sampling of high-impedance sources without relaxing conversion speed. See the register description for further information. Total sampling time is given by:

Figure 2. ADC Timing Diagram - Single Conversion With Delays

In Free-Running mode, a new conversion will be started immediately after the conversion completes, while the STCONV bit is ‘1’. The sampling rate RS in Free-Running mode is calculated by:


Figure 3. ADC Timing Diagram - Free-Running Conversion