It represents how data are transmitted concerning clock generation. The clock polarity and the clock phase are the ones important for data modes. By clock polarity, one can understand the level of the signal which can be low while in the Idle state and will start with a rising edge when transmitting data, or it can be high while in Idle state and will start with a falling when exchanging data. Depending on the phase, the data are generated or sampled concerning the clock on the channel: On a rising or a falling edge. See the figure below.
Both the host and the client devices must be configured in the same way, so one can decode correctly what the other encoded. Data modes can be selected by changing the value of the MODE[1:0] bit field from the CTRLB register.
Until now, the examples were based on SPI Mode 0 because there was no change made to these bits and that is the default value of the bits.
Below is an example of how to configure the SPI in Data Mode 3, based on the normal/basic host SPI Initialization mode presented in Sending Data as a Host SPI Device. The only difference is the change of the data transmission type:
SPI0.CTRLB |= SPI_MODE_3_gc;
An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here:
