Bit Rate Generator

The Bite Rate Generator unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note that Slaves may prolong the SCL low period, thereby reducing the average TWI bus clock frequency. The SCL frequency is generated according to the following equation.

SCL⁢frequency=CPU⁢ ⁢ ⁢Clock⁢frequency16+2(TWBR)−4TWPS

TWPS is located in TWISR, which is in the same register as where the TWI Status bits are. TWPS is therefore chosen to be set to 0 in this application to simplify the handling of the Status bits, and only TWBR is utilized to achieve the desired speed on SCL. The following table shows a selection of pre-calculated TWBR values based on CPU and SCL frequencies.

Table 1. CPU and SCL Frequencies versus Bit Rate Generator Register Settings
CPU Clock Frequency [MHz] TWBR TWPS SCL Frequency [kHz]
16 12 0 400
16 72 0 100
14.4 10 0 400
14.4 64 0 100
12 7 0 400
12 52 0 100
8 2 0 400
8 32 0 100
4 12 0 100
3.6 10 0 100
2 2 0 100
2 12 0 50
1 2 0 50
Parent topic: The AVR TWI Module