DDR4

Automatic initialization of DDR4 memory involves the following steps:

  1. 1.Training logic performs HS_IO_CLK-to-SYS_CLK training.
  2. 2.Training logic performs CMD/ADDR to REF_CLK training.
  3. 3.DDR controller waits for the PHY to be ready. At this point, it is assumed that the PHY outputs stable clocks and signal levels at this point.
  4. 4.Controller asserts RESET_N and CKE low.
  5. 5.Controller deasserts RESET_N after 200 μs, and then deasserts CKE after an additional 600 μs.
  6. 6.Controller waits for tXPR.
  7. 7.Controller writes to RCW and BCW if RDIMM/LRDIMM is used.
  8. 8.MRS command is sent to the following mode registers (in order): MR3, MR6, MR5, MR4, MR2, MR1, and MR0.
  9. 9.Controller waits for 128 clock cycles (geardown mode). Controller waits for an additional 512 clock cycles for the ZQCL (long) command to be sent to each rank independently to calibrate the RTT and RON values.
  10. 10.Training logic performs write leveling.
  11. 11.Training logic performs DQS gate training.
  12. 12.Training logic aligns read DQ bits.
  13. 13.Training logic aligns read DQS to DQ.
  14. 14.Write calibration is performed.
  15. 15.Normal operation begins.

The controller reinitializes the SDRAM memory when a low-to-high transition is detected on the reinitialization control signal (CTRLR_INIT).

The following figure shows the DDR4 automatic initialization flow.

Figure 1. Automatic Initialization Flow for DDR4 Memory