DRAM Initialization

After the first step, the controller starts the JEDEC compliant initialization sequence. The controller initializes the DRAM devices by writing to their mode registers. The DRAM device is initialized by issuing MRS command to mode registers as per the JEDEC specification. For example, the MRS command is issued on the DRAM interface by asserting CS_N=0, RAS_N=0, CAS_N=0, and WE_N=0. The Mode register address is sent on BA pins and the Mode register data is sent on DRAM ADDR pins.

The controller must drive these signals accordingly on the DFI interface. The latency in the PHY is identical on all of the control interface signals. The controller must meet the timing of the DRAM interface on the DFI interface.

Figure 1 shows the DFI to DRAM latency and is an example of how the memory controller drives the DFI interface to obtain the desired functionality and timing on the DRAM interface.

In the DFI Specification, there is a single timing parameter (tCTRL_DELAY, which needs to be set in the DDR controller) for all of the control interface. The controller must implement this DFI timing inside it.

The latency seen in Figure 1 is the minimal latency observed from DFI command to DRAM command. For this example tCTRL_DELAY was set to 0. Any tCTRL_DELAY value set by the controller is added to the latency shown in Figure 1.

Note: The DDR3 example is used to show the simulation.
Figure 1. DFI To DRAM Control Interface Timing Relationship