Simulating the DDR Subsystem

Libero SoC provides a simulation model for the DDR subsystem, which includes a training sequence (three simulation modes are supported as mentioned in Simulation Options). For simulating the DDR subsystem, the DDR DRAM interface must be connected to a third-party DDR memory simulation model in a testbench. Memory vendors such as Micron, Samsung, and Hynix provide downloadable, JEDEC-compliant simulation models for memory devices. For information about setting up and running the simulation, see Accessing DDR Subsystem Through AXI4 Interface.

Note: SmartDesign Testbench does not support instantiation of SystemVerilog testbenches for DDR models. To use SystemVerilog, create an HDL testbench instead of a SmartDesign testbench, and select System Verilog in Libero Project settings.